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Sparc: Remove Is64Bit field from SparcTargetMachine (#157400)
Directly use the triple instead of having an additional field.
1 parent 1bd3cc2 commit 16fddf8

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4 files changed

+19
-20
lines changed

4 files changed

+19
-20
lines changed

llvm/lib/Target/Sparc/SparcSubtarget.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(
3131
// Determine default and user specified characteristics
3232
std::string CPUName = std::string(CPU);
3333
if (CPUName.empty())
34-
CPUName = (Is64Bit) ? "v9" : "v8";
34+
CPUName = getTargetTriple().isSPARC64() ? "v9" : "v8";
3535

3636
if (TuneCPU.empty())
3737
TuneCPU = CPUName;
@@ -47,10 +47,10 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(
4747
}
4848

4949
SparcSubtarget::SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU,
50-
const StringRef &FS, const TargetMachine &TM,
51-
bool is64Bit)
50+
const StringRef &FS, const TargetMachine &TM)
5251
: SparcGenSubtargetInfo(TM.getTargetTriple(), CPU, TuneCPU, FS),
53-
ReserveRegister(TM.getMCRegisterInfo()->getNumRegs()), Is64Bit(is64Bit),
52+
ReserveRegister(TM.getMCRegisterInfo()->getNumRegs()),
53+
Is64Bit(TM.getTargetTriple().isSPARC64()),
5454
InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
5555
TLInfo(TM, *this), FrameLowering(*this) {
5656
TSInfo = std::make_unique<SparcSelectionDAGInfo>();

llvm/lib/Target/Sparc/SparcSubtarget.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
3636

3737
virtual void anchor();
3838

39-
bool Is64Bit;
39+
const bool Is64Bit;
4040

4141
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
4242
bool ATTRIBUTE = DEFAULT;
@@ -49,7 +49,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
4949

5050
public:
5151
SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU,
52-
const StringRef &FS, const TargetMachine &TM, bool is64bit);
52+
const StringRef &FS, const TargetMachine &TM);
5353

5454
~SparcSubtarget() override;
5555

llvm/lib/Target/Sparc/SparcTargetMachine.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,9 @@ static cl::opt<bool>
3838
BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true),
3939
cl::desc("Relax out of range conditional branches"));
4040

41-
static std::string computeDataLayout(const Triple &T, bool is64Bit) {
41+
static std::string computeDataLayout(const Triple &T) {
42+
const bool is64Bit = T.isSPARC64();
43+
4244
// Sparc is typically big endian, but some are little.
4345
std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
4446
Ret += "-m:e";
@@ -107,15 +109,14 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
107109
const TargetOptions &Options,
108110
std::optional<Reloc::Model> RM,
109111
std::optional<CodeModel::Model> CM,
110-
CodeGenOptLevel OL, bool JIT,
111-
bool is64bit)
112+
CodeGenOptLevel OL, bool JIT)
112113
: CodeGenTargetMachineImpl(
113-
T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
114+
T, computeDataLayout(TT), TT, CPU, FS, Options,
114115
getEffectiveRelocModel(RM),
115-
getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM), is64bit,
116-
JIT),
116+
getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM),
117+
TT.isSPARC64(), JIT),
117118
OL),
118-
TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
119+
TLOF(std::make_unique<SparcELFTargetObjectFile>()) {
119120
initAsmInfo();
120121
}
121122

@@ -148,8 +149,7 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const {
148149
// creation will depend on the TM and the code generation flags on the
149150
// function that reside in TargetOptions.
150151
resetTargetOptions(F);
151-
I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this,
152-
this->is64Bit);
152+
I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this);
153153
}
154154
return I.get();
155155
}
@@ -212,7 +212,7 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
212212
std::optional<Reloc::Model> RM,
213213
std::optional<CodeModel::Model> CM,
214214
CodeGenOptLevel OL, bool JIT)
215-
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
215+
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT) {}
216216

217217
void SparcV9TargetMachine::anchor() { }
218218

@@ -222,7 +222,7 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
222222
std::optional<Reloc::Model> RM,
223223
std::optional<CodeModel::Model> CM,
224224
CodeGenOptLevel OL, bool JIT)
225-
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
225+
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT) {}
226226

227227
void SparcelTargetMachine::anchor() {}
228228

@@ -232,4 +232,4 @@ SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
232232
std::optional<Reloc::Model> RM,
233233
std::optional<CodeModel::Model> CM,
234234
CodeGenOptLevel OL, bool JIT)
235-
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
235+
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT) {}

llvm/lib/Target/Sparc/SparcTargetMachine.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,15 +23,14 @@ namespace llvm {
2323

2424
class SparcTargetMachine : public CodeGenTargetMachineImpl {
2525
std::unique_ptr<TargetLoweringObjectFile> TLOF;
26-
bool is64Bit;
2726
mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
2827

2928
public:
3029
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
3130
StringRef FS, const TargetOptions &Options,
3231
std::optional<Reloc::Model> RM,
3332
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
34-
bool JIT, bool is64bit);
33+
bool JIT);
3534
~SparcTargetMachine() override;
3635

3736
const SparcSubtarget *getSubtargetImpl(const Function &F) const override;

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