Skip to content

Commit 1d7ec60

Browse files
topperctopperc
authored
[RISCV] Improve formatting in RISCVInstrInfoVPseudos.td. NFC (#161470)
Primarily focused on changes from RISCVVPseudo recently inheriting from Pseudo.
1 parent 49603bd commit 1d7ec60

File tree

1 file changed

+22
-30
lines changed

1 file changed

+22
-30
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 22 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -554,7 +554,8 @@ defset list<VTypeInfoToWide> AllWidenableBF16ToFloatVectors = {
554554
// This represents the information we need in codegen for each pseudo.
555555
// The definition should be consistent with `struct PseudoInfo` in
556556
// RISCVInstrInfo.h.
557-
class RISCVVPseudo<dag outs, dag ins, list<dag> pattern = [], string opcodestr = "", string argstr = "">
557+
class RISCVVPseudo<dag outs, dag ins, list<dag> pattern = [],
558+
string opcodestr = "", string argstr = "">
558559
: Pseudo<outs, ins, pattern, opcodestr, argstr> {
559560
Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
560561
Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
@@ -1010,8 +1011,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
10101011
class VPseudoNullaryMask<VReg RegClass> :
10111012
RISCVVPseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
10121013
(ins GetVRegNoV0<RegClass>.R:$passthru,
1013-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
1014-
[]> {
1014+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
10151015
let mayLoad = 0;
10161016
let mayStore = 0;
10171017
let hasSideEffects = 0;
@@ -1190,8 +1190,7 @@ class VPseudoBinaryNoMask<VReg RetClass,
11901190
bits<2> TargetConstraintType = 1,
11911191
DAGOperand sewop = sew> :
11921192
RISCVVPseudo<(outs RetClass:$rd),
1193-
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew),
1194-
[]> {
1193+
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew)> {
11951194
let mayLoad = 0;
11961195
let mayStore = 0;
11971196
let hasSideEffects = 0;
@@ -1227,8 +1226,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
12271226
bits<2> TargetConstraintType = 1> :
12281227
RISCVVPseudo<(outs RetClass:$rd),
12291228
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
1230-
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy),
1231-
[]> {
1229+
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
12321230
let mayLoad = 0;
12331231
let mayStore = 0;
12341232
let hasSideEffects = 0;
@@ -1320,7 +1318,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
13201318
bit Ordered>:
13211319
RISCVVPseudo<(outs),
13221320
(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
1323-
AVL:$vl, sew:$sew),[]>,
1321+
AVL:$vl, sew:$sew)>,
13241322
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
13251323
let mayLoad = 0;
13261324
let mayStore = 1;
@@ -1333,7 +1331,7 @@ class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
13331331
bit Ordered>:
13341332
RISCVVPseudo<(outs),
13351333
(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
1336-
VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
1334+
VMaskOp:$vm, AVL:$vl, sew:$sew)>,
13371335
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
13381336
let mayLoad = 0;
13391337
let mayStore = 1;
@@ -1351,8 +1349,7 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
13511349
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
13521350
(ins GetVRegNoV0<RetClass>.R:$passthru,
13531351
Op1Class:$rs2, Op2Class:$rs1,
1354-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
1355-
[]> {
1352+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
13561353
let mayLoad = 0;
13571354
let mayStore = 0;
13581355
let hasSideEffects = 0;
@@ -1371,8 +1368,7 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
13711368
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
13721369
(ins GetVRegNoV0<RetClass>.R:$passthru,
13731370
Op1Class:$rs2, Op2Class:$rs1,
1374-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
1375-
[]> {
1371+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
13761372
let mayLoad = 0;
13771373
let mayStore = 0;
13781374
let hasSideEffects = 0;
@@ -1414,8 +1410,7 @@ class VPseudoBinaryMOutMask<VReg RetClass,
14141410
RISCVVPseudo<(outs RetClass:$rd),
14151411
(ins RetClass:$passthru,
14161412
Op1Class:$rs2, Op2Class:$rs1,
1417-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
1418-
[]> {
1413+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
14191414
let mayLoad = 0;
14201415
let mayStore = 0;
14211416
let hasSideEffects = 0;
@@ -1438,8 +1433,7 @@ class VPseudoTiedBinaryMask<VReg RetClass,
14381433
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
14391434
(ins GetVRegNoV0<RetClass>.R:$passthru,
14401435
Op2Class:$rs1,
1441-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),
1442-
[]> {
1436+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
14431437
let mayLoad = 0;
14441438
let mayStore = 0;
14451439
let hasSideEffects = 0;
@@ -1546,8 +1540,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
15461540
bits<2> TargetConstraintType = 1> :
15471541
RISCVVPseudo<(outs RetClass:$rd),
15481542
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
1549-
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy),
1550-
[]> {
1543+
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy)> {
15511544
let mayLoad = 0;
15521545
let mayStore = 0;
15531546
let hasSideEffects = 0;
@@ -1716,8 +1709,8 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
17161709
int EEW,
17171710
bits<4> NF> :
17181711
RISCVVPseudo<(outs),
1719-
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew),
1720-
[]>,
1712+
(ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl,
1713+
sew:$sew)>,
17211714
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
17221715
let mayLoad = 0;
17231716
let mayStore = 1;
@@ -6029,9 +6022,9 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
60296022
PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVLENB.Encoding, X0)>,
60306023
Sched<[WriteRdVLENB]>;
60316024
let Defs = [VL, VTYPE] in {
6032-
def PseudoReadVLENBViaVSETVLIX0 : Pseudo<(outs GPRNoX0:$rd), (ins uimm5:$shamt),
6033-
[]>,
6034-
Sched<[WriteVSETVLI, ReadVSETVLI]>;
6025+
def PseudoReadVLENBViaVSETVLIX0 : Pseudo<(outs GPRNoX0:$rd),
6026+
(ins uimm5:$shamt), []>,
6027+
Sched<[WriteVSETVLI, ReadVSETVLI]>;
60356028
}
60366029
}
60376030

@@ -6694,14 +6687,14 @@ defm PseudoVID : VPseudoVID_V;
66946687
let Predicates = [HasVInstructions] in {
66956688
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
66966689
let HasSEWOp = 1, BaseInstr = VMV_X_S in
6697-
def PseudoVMV_X_S:
6690+
def PseudoVMV_X_S :
66986691
RISCVVPseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew)>,
66996692
Sched<[WriteVMovXS, ReadVMovXS]>;
67006693
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,
67016694
Constraints = "$rd = $passthru" in
6702-
def PseudoVMV_S_X: RISCVVPseudo<(outs VR:$rd),
6703-
(ins VR:$passthru, GPR:$rs1, AVL:$vl, sew:$sew),
6704-
[]>,
6695+
def PseudoVMV_S_X :
6696+
RISCVVPseudo<(outs VR:$rd),
6697+
(ins VR:$passthru, GPR:$rs1, AVL:$vl, sew:$sew)>,
67056698
Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>;
67066699
}
67076700
} // Predicates = [HasVInstructions]
@@ -6721,8 +6714,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
67216714
Constraints = "$rd = $passthru" in
67226715
def "PseudoVFMV_S_" # f.FX :
67236716
RISCVVPseudo<(outs VR:$rd),
6724-
(ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew),
6725-
[]>,
6717+
(ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew)>,
67266718
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
67276719
}
67286720
}

0 commit comments

Comments
 (0)