[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.

As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.

Author: ArcaneNibble

clang/test/Driver/print-supported-extensions-riscv.c

@@ -166,6 +166,7 @@
 // CHECK-NEXT:     xtheadsync           1.0       'xtheadsync' (T-Head multicore synchronization instructions)
 // CHECK-NEXT:     xtheadvdot           1.0       'xtheadvdot' (T-Head Vector Extensions for Dot)
 // CHECK-NEXT:     xventanacondops      1.0       'XVentanaCondOps' (Ventana Conditional Ops)
+// CHECK-NEXT:     xwchc                2.2       'Xwchc' (WCH/QingKe additional compressed opcodes)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
 // CHECK-NEXT:     zicfilp              0.4       'Zicfilp' (Landing pad)

llvm/docs/RISCVUsage.rst

@@ -396,6 +396,9 @@ The current vendor extensions supported are:
 ``XSfcease``
   LLVM implements `the SiFive sf.cease instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
 
+``Xwchc``
+  LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".
+
 Experimental C Intrinsics
 =========================
 

llvm/docs/ReleaseNotes.rst

@@ -197,6 +197,8 @@ Changes to the RISC-V Backend
   fully compatible with objects produced prior to this change. The mapping
   (ABI) used is recorded as an ELF attribute.
 * Ztso is no longer experimental.
+* The WCH / Nanjing Qinheng Microelectronics QingKe "XW" compressed opcodes are
+  supported under the name "Xwchc".
 
 Changes to the WebAssembly Backend
 ----------------------------------

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -809,6 +809,26 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm5Lsb0() const {
+    if (!isImm())
+      return false;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isShiftedUInt<4, 1>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm6Lsb0() const {
+    if (!isImm())
+      return false;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isShiftedUInt<5, 1>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm7Lsb00() const {
     if (!isImm())
       return false;
@@ -1502,6 +1522,14 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 1, (1 << 5) - 1,
         "immediate must be in [0xfffe0, 0xfffff] or");
+  case Match_InvalidUImm5Lsb0:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, 0, (1 << 5) - 2,
+        "immediate must be a multiple of 2 bytes in the range");
+  case Match_InvalidUImm6Lsb0:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, 0, (1 << 6) - 2,
+        "immediate must be a multiple of 2 bytes in the range");
   case Match_InvalidUImm7Lsb00:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 7) - 4,

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -646,6 +646,9 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
   TRY_TO_DECODE_FEATURE(
       RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
       "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
+  TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
+                           DecoderTableXwchc16,
+                           "WCH QingKe XW custom opcode table");
   TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
                            "RISCV_C table (16-bit Instruction)");
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -269,7 +269,9 @@ enum OperandType : unsigned {
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
+  OPERAND_UIMM5_LSB0,
   OPERAND_UIMM6,
+  OPERAND_UIMM6_LSB0,
   OPERAND_UIMM7,
   OPERAND_UIMM7_LSB00,
   OPERAND_UIMM8_LSB00,

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1210,6 +1210,16 @@ def HasVendorXCVbi
       AssemblerPredicate<(all_of FeatureVendorXCVbi),
                          "'XCVbi' (CORE-V Immediate Branching)">;
 
+// WCH / Nanjing Qinheng Microelectronics Extension(s)
+
+def FeatureVendorXwchc
+    : RISCVExtension<"xwchc", 2, 2,
+                     "'Xwchc' (WCH/QingKe additional compressed opcodes)">;
+def HasVendorXwchc
+    : Predicate<"Subtarget->hasVendorXwchc()">,
+      AssemblerPredicate<(all_of FeatureVendorXwchc),
+                         "'Xwchc' (WCH/QingKe additional compressed opcodes)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -2386,6 +2386,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         case RISCVOp::OPERAND_UIMM2_LSB0:
           Ok = isShiftedUInt<1, 1>(Imm);
           break;
+        case RISCVOp::OPERAND_UIMM5_LSB0:
+          Ok = isShiftedUInt<4, 1>(Imm);
+          break;
+        case RISCVOp::OPERAND_UIMM6_LSB0:
+          Ok = isShiftedUInt<5, 1>(Imm);
+          break;
         case RISCVOp::OPERAND_UIMM7_LSB00:
           Ok = isShiftedUInt<5, 2>(Imm);
           break;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2080,6 +2080,7 @@ include "RISCVInstrInfoXTHead.td"
 include "RISCVInstrInfoXSf.td"
 include "RISCVInstrInfoSFB.td"
 include "RISCVInstrInfoXCV.td"
+include "RISCVInstrInfoXwch.td"
 
 //===----------------------------------------------------------------------===//
 // Global ISel

llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td

@@ -0,0 +1,199 @@
+//===-- RISCVInstrInfoXwch.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extension(s) defined by WCH.
+//
+//===----------------------------------------------------------------------===//
+
+class QKStackInst<bits<2> funct2, dag outs, dag ins,
+                  string opcodestr, string argstr>
+    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<3> rd_rs2;
+
+  let Inst{15-11} = 0b10000;
+  let Inst{6-5} = funct2;
+  let Inst{4-2} = rd_rs2;
+  let Inst{1-0} = 0b00;
+}
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm4_with_predicate : RISCVUImmLeafOp<4> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isUInt<4>(Imm);
+  }];
+}
+
+def uimm5_with_predicate : RISCVUImmLeafOp<5> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isUInt<5>(Imm);
+  }];
+}
+
+// A 5-bit unsigned immediate where the least significant bit is zero.
+def uimm5_lsb0 : RISCVOp,
+                 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 1>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<5, "Lsb0">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_UIMM5_LSB0";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedUInt<4, 1>(Imm);
+  }];
+}
+
+// A 6-bit unsigned immediate where the least significant bit is zero.
+def uimm6_lsb0 : RISCVOp,
+                 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 1>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<6, "Lsb0">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_UIMM6_LSB0";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedUInt<5, 1>(Imm);
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc" in {
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),
+                          (ins GPRCMem:$rs1, uimm5_with_predicate:$imm),
+                          "qk.c.lbu", "$rd, ${imm}(${rs1})">,
+               Sched<[WriteLDB, ReadMemBase]> {
+  bits<5> imm;
+  let Inst{12} = imm{0};
+  let Inst{11-10} = imm{4-3};
+  let Inst{6-5} = imm{2-1};
+}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def QK_C_SB : RVInst16CS<0b101, 0b00, (outs),
+                         (ins GPRC:$rs2, GPRCMem:$rs1,
+                              uimm5_with_predicate:$imm),
+                         "qk.c.sb", "$rs2, ${imm}(${rs1})">,
+              Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
+  bits<5> imm;
+  let Inst{12} = imm{0};
+  let Inst{11-10} = imm{4-3};
+  let Inst{6-5} = imm{2-1};
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def QK_C_LHU : RVInst16CL<0b001, 0b10, (outs GPRC:$rd),
+                          (ins GPRCMem:$rs1, uimm6_lsb0:$imm),
+                          "qk.c.lhu", "$rd, ${imm}(${rs1})">,
+               Sched<[WriteLDH, ReadMemBase]> {
+  bits<6> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{2-1};
+}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def QK_C_SH : RVInst16CS<0b101, 0b10, (outs),
+                         (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
+                         "qk.c.sh", "$rs2, ${imm}(${rs1})">,
+              Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
+  bits<6> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6-5} = imm{2-1};
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
+                             (ins SPMem:$rs1, uimm4_with_predicate:$imm),
+                             "qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">,
+                 Sched<[WriteLDB, ReadMemBase]> {
+  bits<4> imm;
+  let Inst{10-7} = imm;
+}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def QK_C_SBSP : QKStackInst<0b10, (outs),
+                            (ins GPRC:$rd_rs2, SPMem:$rs1,
+                                 uimm4_with_predicate:$imm),
+                            "qk.c.sbsp", "$rd_rs2, ${imm}(${rs1})">,
+                Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
+  bits<4> imm;
+  let Inst{10-7} = imm;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2),
+                             (ins SPMem:$rs1, uimm5_lsb0:$imm),
+                             "qk.c.lhusp", "$rd_rs2, ${imm}(${rs1})">,
+                 Sched<[WriteLDH, ReadMemBase]> {
+  bits<5> imm;
+  let Inst{10-8} = imm{3-1};
+  let Inst{7} = imm{4};
+}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def QK_C_SHSP : QKStackInst<0b11, (outs),
+                            (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0:$imm),
+                            "qk.c.shsp", "$rd_rs2, ${imm}(${rs1})">,
+                Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
+  bits<5> imm;
+  let Inst{10-8} = imm{3-1};
+  let Inst{7} = imm{4};
+}
+
+} // Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc"
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let EmitPriority = 0 in {
+let Predicates = [HasVendorXwchc] in {
+def : InstAlias<"qk.c.lbu $rd, (${rs1})", (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, 0)>;
+def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>;
+def : InstAlias<"qk.c.lhu $rd, (${rs1})", (QK_C_LHU GPRC:$rd, GPRCMem:$rs1, 0)>;
+def : InstAlias<"qk.c.sh $rs2, (${rs1})", (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, 0)>;
+def : InstAlias<"qk.c.lbusp $rd, (${rs1})", (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, 0)>;
+def : InstAlias<"qk.c.sbsp $rs2, (${rs1})", (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, 0)>;
+def : InstAlias<"qk.c.lhusp $rd, (${rs1})", (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, 0)>;
+def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)>;
+}
+}
+
+//===----------------------------------------------------------------------===/
+// Compress Instruction tablegen backend.
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasVendorXwchc] in {
+def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm5_with_predicate:$imm),
+                  (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, uimm5_with_predicate:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm),
+                  (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm),
+                  (QK_C_LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
+                  (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm)>;
+def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1,   uimm4_with_predicate:$imm),
+                  (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4_with_predicate:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1,   uimm4_with_predicate:$imm),
+                  (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4_with_predicate:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, SPMem:$rs1,   uimm5_lsb0:$imm),
+                  (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, SPMem:$rs1,   uimm5_lsb0:$imm),
+                  (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm)>;
+}