[RISCV] Add Zfa test cases for strict ONE and UEQ comparisons. NFC

These correspond to islessgreater and it inverse.

Author: topperc

llvm/test/CodeGen/RISCV/double-zfa.ll

@@ -119,6 +119,31 @@ define i32 @fcmp_ole_q(double %a, double %b) nounwind strictfp {
   ret i32 %2
 }
 
+define i32 @fcmp_one_q(double %a, double %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_one_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.d a0, fa0, fa1
+; CHECK-NEXT:    fltq.d a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"one", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ueq_q(double %a, double %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_ueq_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.d a0, fa0, fa1
+; CHECK-NEXT:    fltq.d a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
 define i64 @fmvh_x_d(double %fa) {
 ; RV32IDZFA-LABEL: fmvh_x_d:
 ; RV32IDZFA:       # %bb.0:

llvm/test/CodeGen/RISCV/float-zfa.ll

@@ -119,3 +119,28 @@ define i32 @fcmp_ole_q(float %a, float %b) nounwind strictfp {
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
+
+define i32 @fcmp_one_q(float %a, float %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_one_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.s a0, fa0, fa1
+; CHECK-NEXT:    fltq.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ueq_q(float %a, float %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_ueq_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.s a0, fa0, fa1
+; CHECK-NEXT:    fltq.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}

llvm/test/CodeGen/RISCV/half-zfa.ll

@@ -118,3 +118,28 @@ define i32 @fcmp_ole_q(half %a, half %b) nounwind strictfp {
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
+
+define i32 @fcmp_one_q(half %a, half %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_one_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.h a0, fa0, fa1
+; CHECK-NEXT:    fltq.h a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ueq_q(half %a, half %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_ueq_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.h a0, fa0, fa1
+; CHECK-NEXT:    fltq.h a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}