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[InstCombine] Infer nneg on zext when forming from non-negative sext (#70706)
Builds on #67982 which recently introduced the nneg flag on a zext instruction. InstCombine is one of our largest canonicalizers of zext from non-negative sext instructions, so set the flag there.
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18 files changed

+65
-62
lines changed

18 files changed

+65
-62
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1372,8 +1372,11 @@ Instruction *InstCombinerImpl::visitSExt(SExtInst &Sext) {
13721372
unsigned DestBitSize = DestTy->getScalarSizeInBits();
13731373

13741374
// If the value being extended is zero or positive, use a zext instead.
1375-
if (isKnownNonNegative(Src, DL, 0, &AC, &Sext, &DT))
1376-
return CastInst::Create(Instruction::ZExt, Src, DestTy);
1375+
if (isKnownNonNegative(Src, DL, 0, &AC, &Sext, &DT)) {
1376+
auto CI = CastInst::Create(Instruction::ZExt, Src, DestTy);
1377+
CI->setNonNeg(true);
1378+
return CI;
1379+
}
13771380

13781381
// Try to extend the entire expression tree to the wide destination type.
13791382
if (shouldChangeType(SrcTy, DestTy) && canEvaluateSExtd(Src, DestTy)) {

‎llvm/test/Transforms/InstCombine/adjust-for-minmax.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -246,7 +246,7 @@ define <2 x i32> @umin4_vec(<2 x i32> %n) {
246246
define i64 @smax_sext(i32 %a) {
247247
; CHECK-LABEL: @smax_sext(
248248
; CHECK-NEXT: [[NARROW:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0)
249-
; CHECK-NEXT: [[MAX:%.*]] = zext i32 [[NARROW]] to i64
249+
; CHECK-NEXT: [[MAX:%.*]] = zext nneg i32 [[NARROW]] to i64
250250
; CHECK-NEXT: ret i64 [[MAX]]
251251
;
252252
%a_ext = sext i32 %a to i64
@@ -258,7 +258,7 @@ define i64 @smax_sext(i32 %a) {
258258
define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
259259
; CHECK-LABEL: @smax_sext_vec(
260260
; CHECK-NEXT: [[NARROW:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer)
261-
; CHECK-NEXT: [[MAX:%.*]] = zext <2 x i32> [[NARROW]] to <2 x i64>
261+
; CHECK-NEXT: [[MAX:%.*]] = zext nneg <2 x i32> [[NARROW]] to <2 x i64>
262262
; CHECK-NEXT: ret <2 x i64> [[MAX]]
263263
;
264264
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -318,7 +318,7 @@ define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
318318
define i64 @umin_sext(i32 %a) {
319319
; CHECK-LABEL: @umin_sext(
320320
; CHECK-NEXT: [[NARROW:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2)
321-
; CHECK-NEXT: [[MIN:%.*]] = zext i32 [[NARROW]] to i64
321+
; CHECK-NEXT: [[MIN:%.*]] = zext nneg i32 [[NARROW]] to i64
322322
; CHECK-NEXT: ret i64 [[MIN]]
323323
;
324324
%a_ext = sext i32 %a to i64
@@ -330,7 +330,7 @@ define i64 @umin_sext(i32 %a) {
330330
define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
331331
; CHECK-LABEL: @umin_sext_vec(
332332
; CHECK-NEXT: [[NARROW:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
333-
; CHECK-NEXT: [[MIN:%.*]] = zext <2 x i32> [[NARROW]] to <2 x i64>
333+
; CHECK-NEXT: [[MIN:%.*]] = zext nneg <2 x i32> [[NARROW]] to <2 x i64>
334334
; CHECK-NEXT: ret <2 x i64> [[MIN]]
335335
;
336336
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -366,7 +366,7 @@ define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
366366
define i64 @umin_sext2(i32 %a) {
367367
; CHECK-LABEL: @umin_sext2(
368368
; CHECK-NEXT: [[NARROW:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 3)
369-
; CHECK-NEXT: [[MIN:%.*]] = zext i32 [[NARROW]] to i64
369+
; CHECK-NEXT: [[MIN:%.*]] = zext nneg i32 [[NARROW]] to i64
370370
; CHECK-NEXT: ret i64 [[MIN]]
371371
;
372372
%a_ext = sext i32 %a to i64
@@ -378,7 +378,7 @@ define i64 @umin_sext2(i32 %a) {
378378
define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
379379
; CHECK-LABEL: @umin_sext2_vec(
380380
; CHECK-NEXT: [[NARROW:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
381-
; CHECK-NEXT: [[MIN:%.*]] = zext <2 x i32> [[NARROW]] to <2 x i64>
381+
; CHECK-NEXT: [[MIN:%.*]] = zext nneg <2 x i32> [[NARROW]] to <2 x i64>
382382
; CHECK-NEXT: ret <2 x i64> [[MIN]]
383383
;
384384
%a_ext = sext <2 x i32> %a to <2 x i64>

‎llvm/test/Transforms/InstCombine/cast-mul-select.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ define void @PR36225(i32 %a, i32 %b, i1 %c1, i3 %v1, i3 %v2) {
193193
; CHECK-NEXT: ]
194194
; CHECK: for.end:
195195
; CHECK-NEXT: [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ]
196-
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[H]] to i32
196+
; CHECK-NEXT: [[CONV:%.*]] = zext nneg i8 [[H]] to i32
197197
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]]
198198
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]]
199199
; CHECK: exit2:
@@ -224,7 +224,7 @@ define void @PR36225(i32 %a, i32 %b, i1 %c1, i3 %v1, i3 %v2) {
224224
; DBGINFO: for.end:
225225
; DBGINFO-NEXT: [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ], !dbg [[DBG100:![0-9]+]]
226226
; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i8 [[H]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG100]]
227-
; DBGINFO-NEXT: [[CONV:%.*]] = zext i8 [[H]] to i32, !dbg [[DBG101:![0-9]+]]
227+
; DBGINFO-NEXT: [[CONV:%.*]] = zext nneg i8 [[H]] to i32, !dbg [[DBG101:![0-9]+]]
228228
; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[CONV]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG101]]
229229
; DBGINFO-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]], !dbg [[DBG102:![0-9]+]]
230230
; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META93:![0-9]+]], metadata !DIExpression()), !dbg [[DBG102]]

‎llvm/test/Transforms/InstCombine/icmp-ext-ext.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -289,7 +289,7 @@ define i1 @zext_sext_eq_known_nonneg(i8 %x, i8 %y) {
289289
define i1 @zext_sext_sle_known_nonneg_op0_narrow(i8 %x, i16 %y) {
290290
; CHECK-LABEL: @zext_sext_sle_known_nonneg_op0_narrow(
291291
; CHECK-NEXT: [[N:%.*]] = and i8 [[X:%.*]], 12
292-
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i16
292+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i8 [[N]] to i16
293293
; CHECK-NEXT: [[C:%.*]] = icmp sle i16 [[TMP1]], [[Y:%.*]]
294294
; CHECK-NEXT: ret i1 [[C]]
295295
;
@@ -370,7 +370,7 @@ define <2 x i1> @sext_zext_sge_known_nonneg_op0_narrow(<2 x i5> %x, <2 x i8> %y)
370370
define i1 @sext_zext_uge_known_nonneg_op0_wide(i16 %x, i8 %y) {
371371
; CHECK-LABEL: @sext_zext_uge_known_nonneg_op0_wide(
372372
; CHECK-NEXT: [[N:%.*]] = and i8 [[Y:%.*]], 12
373-
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i16
373+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i8 [[N]] to i16
374374
; CHECK-NEXT: [[C:%.*]] = icmp ule i16 [[TMP1]], [[X:%.*]]
375375
; CHECK-NEXT: ret i1 [[C]]
376376
;

‎llvm/test/Transforms/InstCombine/memcpy-from-global.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,25 +8,25 @@ define float @test1(i32 %hash, float %x, float %y, float %z, float %w) {
88
; CHECK-NEXT: entry:
99
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[HASH:%.*]], 2
1010
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], 124
11-
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[TMP5]] to i64
11+
; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[TMP5]] to i64
1212
; CHECK-NEXT: [[TMP753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]]
1313
; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP753]], align 4
1414
; CHECK-NEXT: [[TMP11:%.*]] = fmul float [[TMP9]], [[X:%.*]]
1515
; CHECK-NEXT: [[TMP13:%.*]] = fadd float [[TMP11]], 0.000000e+00
1616
; CHECK-NEXT: [[TMP17_SUM52:%.*]] = or i32 [[TMP5]], 1
17-
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP17_SUM52]] to i64
17+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[TMP17_SUM52]] to i64
1818
; CHECK-NEXT: [[TMP1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]]
1919
; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[TMP1851]], align 4
2020
; CHECK-NEXT: [[TMP21:%.*]] = fmul float [[TMP19]], [[Y:%.*]]
2121
; CHECK-NEXT: [[TMP23:%.*]] = fadd float [[TMP21]], [[TMP13]]
2222
; CHECK-NEXT: [[TMP27_SUM50:%.*]] = or i32 [[TMP5]], 2
23-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP27_SUM50]] to i64
23+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP27_SUM50]] to i64
2424
; CHECK-NEXT: [[TMP2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]]
2525
; CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[TMP2849]], align 4
2626
; CHECK-NEXT: [[TMP31:%.*]] = fmul float [[TMP29]], [[Z:%.*]]
2727
; CHECK-NEXT: [[TMP33:%.*]] = fadd float [[TMP31]], [[TMP23]]
2828
; CHECK-NEXT: [[TMP37_SUM48:%.*]] = or i32 [[TMP5]], 3
29-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP37_SUM48]] to i64
29+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP37_SUM48]] to i64
3030
; CHECK-NEXT: [[TMP3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]]
3131
; CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP3847]], align 4
3232
; CHECK-NEXT: [[TMP41:%.*]] = fmul float [[TMP39]], [[W:%.*]]

‎llvm/test/Transforms/InstCombine/minmax-intrinsics.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -217,7 +217,7 @@ define i8 @umin_zext_uses(i5 %x, i5 %y) {
217217
define i8 @smax_sext_constant(i5 %x) {
218218
; CHECK-LABEL: @smax_sext_constant(
219219
; CHECK-NEXT: [[TMP1:%.*]] = call i5 @llvm.smax.i5(i5 [[X:%.*]], i5 7)
220-
; CHECK-NEXT: [[M:%.*]] = zext i5 [[TMP1]] to i8
220+
; CHECK-NEXT: [[M:%.*]] = zext nneg i5 [[TMP1]] to i8
221221
; CHECK-NEXT: ret i8 [[M]]
222222
;
223223
%e = sext i5 %x to i8
@@ -322,7 +322,7 @@ define i8 @umax_zext_constant_big(i5 %x) {
322322
define i8 @umin_sext_constant(i5 %x) {
323323
; CHECK-LABEL: @umin_sext_constant(
324324
; CHECK-NEXT: [[TMP1:%.*]] = call i5 @llvm.umin.i5(i5 [[X:%.*]], i5 7)
325-
; CHECK-NEXT: [[M:%.*]] = zext i5 [[TMP1]] to i8
325+
; CHECK-NEXT: [[M:%.*]] = zext nneg i5 [[TMP1]] to i8
326326
; CHECK-NEXT: ret i8 [[M]]
327327
;
328328
%e = sext i5 %x to i8

‎llvm/test/Transforms/InstCombine/narrow-math.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ define i64 @test2(i32 %V) {
141141
; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
142142
; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
143143
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]]
144-
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
144+
; CHECK-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[ADD]] to i64
145145
; CHECK-NEXT: ret i64 [[ZEXT]]
146146
;
147147
%call1 = call i32 @callee(), !range !0
@@ -172,7 +172,7 @@ define i64 @test4(i32 %V) {
172172
; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
173173
; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
174174
; CHECK-NEXT: [[ADD:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]]
175-
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
175+
; CHECK-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[ADD]] to i64
176176
; CHECK-NEXT: ret i64 [[ZEXT]]
177177
;
178178
%call1 = call i32 @callee(), !range !0
@@ -480,7 +480,7 @@ define i64 @test12(i32 %V) {
480480
; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]]
481481
; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]]
482482
; CHECK-NEXT: [[NARROW:%.*]] = mul nsw i32 [[CALL1]], [[CALL2]]
483-
; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64
483+
; CHECK-NEXT: [[ADD:%.*]] = zext nneg i32 [[NARROW]] to i64
484484
; CHECK-NEXT: ret i64 [[ADD]]
485485
;
486486
%call1 = call i32 @callee(), !range !1
@@ -614,7 +614,7 @@ define i64 @test18(i32 %V) {
614614
define i64 @test19(i32 %V) {
615615
; CHECK-LABEL: @test19(
616616
; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
617-
; CHECK-NEXT: [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64
617+
; CHECK-NEXT: [[SEXT1:%.*]] = zext nneg i32 [[CALL1]] to i64
618618
; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i64 -2147481648, [[SEXT1]]
619619
; CHECK-NEXT: ret i64 [[SUB]]
620620
;

‎llvm/test/Transforms/InstCombine/select_meta.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ define i32 @foo2(i32, i32) local_unnamed_addr #0 {
6464
define i64 @test43(i32 %a) nounwind {
6565
; CHECK-LABEL: @test43(
6666
; CHECK-NEXT: [[NARROW:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0)
67-
; CHECK-NEXT: [[MAX:%.*]] = zext i32 [[NARROW]] to i64
67+
; CHECK-NEXT: [[MAX:%.*]] = zext nneg i32 [[NARROW]] to i64
6868
; CHECK-NEXT: ret i64 [[MAX]]
6969
;
7070
%a_ext = sext i32 %a to i64

‎llvm/test/Transforms/InstCombine/sext.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ declare void @use_vec(<2 x i5>)
1212
define i64 @test1(i32 %x) {
1313
; CHECK-LABEL: @test1(
1414
; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]]
15-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
15+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64
1616
; CHECK-NEXT: ret i64 [[S]]
1717
;
1818
%t = call i32 @llvm.ctpop.i32(i32 %x)
@@ -23,7 +23,7 @@ define i64 @test1(i32 %x) {
2323
define i64 @test2(i32 %x) {
2424
; CHECK-LABEL: @test2(
2525
; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
26-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
26+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64
2727
; CHECK-NEXT: ret i64 [[S]]
2828
;
2929
%t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
@@ -34,7 +34,7 @@ define i64 @test2(i32 %x) {
3434
define i64 @test3(i32 %x) {
3535
; CHECK-LABEL: @test3(
3636
; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
37-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
37+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64
3838
; CHECK-NEXT: ret i64 [[S]]
3939
;
4040
%t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
@@ -45,7 +45,7 @@ define i64 @test3(i32 %x) {
4545
define i64 @test4(i32 %x) {
4646
; CHECK-LABEL: @test4(
4747
; CHECK-NEXT: [[T:%.*]] = udiv i32 [[X:%.*]], 3
48-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
48+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64
4949
; CHECK-NEXT: ret i64 [[S]]
5050
;
5151
%t = udiv i32 %x, 3
@@ -56,7 +56,7 @@ define i64 @test4(i32 %x) {
5656
define i64 @test5(i32 %x) {
5757
; CHECK-LABEL: @test5(
5858
; CHECK-NEXT: [[T:%.*]] = urem i32 [[X:%.*]], 30000
59-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
59+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64
6060
; CHECK-NEXT: ret i64 [[S]]
6161
;
6262
%t = urem i32 %x, 30000
@@ -68,7 +68,7 @@ define i64 @test6(i32 %x) {
6868
; CHECK-LABEL: @test6(
6969
; CHECK-NEXT: [[U:%.*]] = lshr i32 [[X:%.*]], 3
7070
; CHECK-NEXT: [[T:%.*]] = mul nuw nsw i32 [[U]], 3
71-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
71+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64
7272
; CHECK-NEXT: ret i64 [[S]]
7373
;
7474
%u = lshr i32 %x, 3
@@ -81,7 +81,7 @@ define i64 @test7(i32 %x) {
8181
; CHECK-LABEL: @test7(
8282
; CHECK-NEXT: [[T:%.*]] = and i32 [[X:%.*]], 511
8383
; CHECK-NEXT: [[U:%.*]] = sub nuw nsw i32 20000, [[T]]
84-
; CHECK-NEXT: [[S:%.*]] = zext i32 [[U]] to i64
84+
; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[U]] to i64
8585
; CHECK-NEXT: ret i64 [[S]]
8686
;
8787
%t = and i32 %x, 511
@@ -296,7 +296,7 @@ define i32 @test17(i1 %x) {
296296
define i32 @test18(i16 %x) {
297297
; CHECK-LABEL: @test18(
298298
; CHECK-NEXT: [[SEL:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0)
299-
; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[SEL]] to i32
299+
; CHECK-NEXT: [[EXT:%.*]] = zext nneg i16 [[SEL]] to i32
300300
; CHECK-NEXT: ret i32 [[EXT]]
301301
;
302302
%cmp = icmp slt i16 %x, 0

‎llvm/test/Transforms/InstCombine/udiv-simplify.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ define i64 @test1_PR2274(i32 %x, i32 %g) nounwind {
2727
; CHECK-LABEL: @test1_PR2274(
2828
; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 30
2929
; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[G:%.*]]
30-
; CHECK-NEXT: [[Z:%.*]] = zext i32 [[R]] to i64
30+
; CHECK-NEXT: [[Z:%.*]] = zext nneg i32 [[R]] to i64
3131
; CHECK-NEXT: ret i64 [[Z]]
3232
;
3333
%y = lshr i32 %x, 30
@@ -39,7 +39,7 @@ define i64 @test2_PR2274(i32 %x, i32 %v) nounwind {
3939
; CHECK-LABEL: @test2_PR2274(
4040
; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 31
4141
; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[V:%.*]]
42-
; CHECK-NEXT: [[Z:%.*]] = zext i32 [[R]] to i64
42+
; CHECK-NEXT: [[Z:%.*]] = zext nneg i32 [[R]] to i64
4343
; CHECK-NEXT: ret i64 [[Z]]
4444
;
4545
%y = lshr i32 %x, 31

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