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[flang][openacc] Keep region when applying data operand conversion
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Similar to D148039 but for the FIR to LLVM IR
conversion pass.

The inner part of the acc.loop has been removed since the rest of the
pipeline is not ready and would raise an error here. This was passing
until now because the acc.loop was discarded completely.

Reviewed By: PeteSteinfeld

Differential Revision: https://reviews.llvm.org/D148057
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clementval committed Apr 12, 2023
1 parent 76e4070 commit 49a813b
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Showing 2 changed files with 17 additions and 25 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -74,8 +74,21 @@ class LegalizeDataOpForLLVMTranslation : public ConvertOpToLLVMPattern<Op> {
}
}

builder.replaceOpWithNewOp<Op>(op, TypeRange(), convertedOperands,
op.getOperation()->getAttrs());
if constexpr (std::is_same_v<Op, acc::ParallelOp> ||
std::is_same_v<Op, acc::DataOp>) {
auto newOp =
builder.create<Op>(op.getLoc(), TypeRange(), convertedOperands,
op.getOperation()->getAttrs());
builder.inlineRegionBefore(op.getRegion(), newOp.getRegion(),
newOp.getRegion().end());
if (failed(builder.convertRegionTypes(&newOp.getOperation()->getRegion(0),
*this->getTypeConverter())))
return failure();
builder.eraseOp(op);
} else {
builder.replaceOpWithNewOp<Op>(op, TypeRange(), convertedOperands,
op.getOperation()->getAttrs());
}

return success();
}
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25 changes: 2 additions & 23 deletions flang/test/Transforms/OpenACC/convert-data-operands-to-llvmir.fir
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
// RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | FileCheck %s
// RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefix=LLVMIR
// RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | fir-opt -split-input-file --fir-to-llvm-ir | FileCheck %s --check-prefix=LLVMIR

fir.global internal @_QFEa : !fir.array<10xf32> {
%0 = fir.undefined !fir.array<10xf32>
Expand Down Expand Up @@ -83,28 +83,6 @@ func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
%1 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFEi"}
acc.parallel copyin(%0: !fir.ref<!fir.array<10xf32>>) {
acc.loop {
%c1_i32 = arith.constant 1 : i32
%2 = fir.convert %c1_i32 : (i32) -> index
%c10_i32 = arith.constant 10 : i32
%3 = fir.convert %c10_i32 : (i32) -> index
%c1 = arith.constant 1 : index
%4 = fir.convert %2 : (index) -> i32
%5:2 = fir.do_loop %arg0 = %2 to %3 step %c1 iter_args(%arg1 = %4) -> (index, i32) {
fir.store %arg1 to %1 : !fir.ref<i32>
%6 = fir.load %1 : !fir.ref<i32>
%7 = fir.convert %6 : (i32) -> f32
%c10_i64 = arith.constant 10 : i64
%c1_i64 = arith.constant 1 : i64
%8 = arith.subi %c10_i64, %c1_i64 : i64
%9 = fir.coordinate_of %0, %8 : (!fir.ref<!fir.array<10xf32>>, i64) -> !fir.ref<f32>
fir.store %7 to %9 : !fir.ref<f32>
%10 = arith.addi %arg0, %c1 : index
%11 = fir.convert %c1 : (index) -> i32
%12 = fir.load %1 : !fir.ref<i32>
%13 = arith.addi %12, %11 : i32
fir.result %10, %13 : index, i32
}
fir.store %5#1 to %1 : !fir.ref<i32>
acc.yield
}
acc.yield
Expand All @@ -116,6 +94,7 @@ func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
// CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
// CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
// CHECK: acc.parallel copyin(%[[CAST]]: !llvm.ptr<array<10 x f32>>) {
// CHECK: acc.loop

// LLVMIR-LABEL: llvm.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
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