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Jessica Paquette
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[AArch64][GlobalISel] Change store value type from p0 -> s64 to import patterns
Similar to the G_PTR_ADD + G_LOAD twiddling we do in `preISelLower`. The imported patterns expect scalars only, so they can't handle things like ``` G_STORE %ptr1, %ptr2 ``` To get around this, use s64 instead. (This probably makes a good portion of the manual selection code for G_STORE dead.) This is a 0.2% geomean code size improvement on CTMark at -Os. (Best is consumer-typeset @ -0.7%) Differential Revision: https://reviews.llvm.org/D95908
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5 files changed

+101
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‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1915,8 +1915,22 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
19151915
}
19161916
return true;
19171917
}
1918-
case TargetOpcode::G_STORE:
1919-
return contractCrossBankCopyIntoStore(I, MRI);
1918+
case TargetOpcode::G_STORE: {
1919+
bool Changed = contractCrossBankCopyIntoStore(I, MRI);
1920+
MachineOperand &SrcOp = I.getOperand(0);
1921+
if (MRI.getType(SrcOp.getReg()).isPointer()) {
1922+
// Allow matching with imported patterns for stores of pointers. Unlike
1923+
// G_LOAD/G_PTR_ADD, we may not have selected all users. So, emit a copy
1924+
// and constrain.
1925+
MachineIRBuilder MIB(I);
1926+
auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp);
1927+
Register NewSrc = Copy.getReg(0);
1928+
SrcOp.setReg(NewSrc);
1929+
RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI);
1930+
Changed = true;
1931+
}
1932+
return Changed;
1933+
}
19201934
case TargetOpcode::G_PTR_ADD:
19211935
return convertPtrAddToAdd(I, MRI);
19221936
case TargetOpcode::G_LOAD: {

‎llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -246,8 +246,9 @@ body: |
246246
liveins: $x0
247247
248248
; CHECK-LABEL: name: store_fi_s64_gpr
249-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
250-
; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
249+
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
250+
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
251+
; CHECK: STRXui [[COPY1]], %stack.0.ptr0, 0 :: (store 8)
251252
%0(p0) = COPY $x0
252253
%1(p0) = G_FRAME_INDEX %stack.0.ptr0
253254
G_STORE %0, %1 :: (store 8)
@@ -613,9 +614,10 @@ body: |
613614
liveins: $x0
614615
; CHECK-LABEL: name: store_adrp_add_low
615616
; CHECK: liveins: $x0
616-
; CHECK: %copy:gpr64 = COPY $x0
617+
; CHECK: %copy:gpr64all = COPY $x0
617618
; CHECK: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x
618-
; CHECK: STRXui %copy, %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store 8 into @x)
619+
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
620+
; CHECK: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store 8 into @x)
619621
%copy:gpr(p0) = COPY $x0
620622
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x
621623
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x

‎llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,9 @@ body: |
5959
6060
; CHECK-LABEL: name: check_sext_not_lost
6161
; CHECK: liveins: $x0
62-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
63-
; CHECK: STRXui [[COPY]], %stack.0.ptr.addr, 0 :: (store 8 into %ir.ptr.addr)
62+
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
63+
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
64+
; CHECK: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store 8 into %ir.ptr.addr)
6465
; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load 8 from %ir.ptr.addr)
6566
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x
6667
; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load 4 from @x)

‎llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,14 @@
33

44
--- |
55
define void @strxrox(i64* %addr) { ret void }
6+
define void @strxrox_p0(i64* %addr) { ret void }
67
define void @strdrox(i64* %addr) { ret void }
78
define void @strwrox(i64* %addr) { ret void }
89
define void @strsrox(i64* %addr) { ret void }
910
define void @strhrox(i64* %addr) { ret void }
1011
define void @strqrox(i64* %addr) { ret void }
1112
define void @shl(i64* %addr) { ret void }
13+
define void @shl_p0(i64* %addr) { ret void }
1214
...
1315

1416
---
@@ -34,6 +36,29 @@ body: |
3436
G_STORE %3, %ptr :: (store 8 into %ir.addr)
3537
...
3638
---
39+
name: strxrox_p0
40+
alignment: 4
41+
legalized: true
42+
regBankSelected: true
43+
tracksRegLiveness: true
44+
machineFunctionInfo: {}
45+
body: |
46+
bb.0:
47+
liveins: $x0, $x1, $x2
48+
; CHECK-LABEL: name: strxrox_p0
49+
; CHECK: liveins: $x0, $x1, $x2
50+
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
51+
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
52+
; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
53+
; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
54+
; CHECK: STRXroX [[COPY3]], [[COPY]], [[COPY1]], 0, 0 :: (store 8 into %ir.addr)
55+
%0:gpr(p0) = COPY $x0
56+
%1:gpr(s64) = COPY $x1
57+
%ptr:gpr(p0) = G_PTR_ADD %0, %1
58+
%3:gpr(p0) = COPY $x2
59+
G_STORE %3, %ptr :: (store 8 into %ir.addr)
60+
...
61+
---
3762
name: strdrox
3863
alignment: 4
3964
legalized: true
@@ -166,3 +191,28 @@ body: |
166191
%ptr:gpr(p0) = G_PTR_ADD %3, %2
167192
%4:gpr(s64) = COPY $x2
168193
G_STORE %4, %ptr :: (store 8 into %ir.addr)
194+
...
195+
---
196+
name: shl_p0
197+
alignment: 4
198+
legalized: true
199+
regBankSelected: true
200+
tracksRegLiveness: true
201+
machineFunctionInfo: {}
202+
body: |
203+
bb.0:
204+
liveins: $x0, $x1, $x2
205+
; CHECK-LABEL: name: shl_p0
206+
; CHECK: liveins: $x0, $x1, $x2
207+
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
208+
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
209+
; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
210+
; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
211+
; CHECK: STRXroX [[COPY3]], [[COPY1]], [[COPY]], 0, 1 :: (store 8 into %ir.addr)
212+
%0:gpr(s64) = COPY $x0
213+
%1:gpr(s64) = G_CONSTANT i64 3
214+
%2:gpr(s64) = G_SHL %0, %1(s64)
215+
%3:gpr(p0) = COPY $x1
216+
%ptr:gpr(p0) = G_PTR_ADD %3, %2
217+
%4:gpr(p0) = COPY $x2
218+
G_STORE %4, %ptr :: (store 8 into %ir.addr)

‎llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,3 +50,29 @@ body: |
5050
%dst:gpr(s64) = COPY $x2
5151
G_STORE %dst, %ptr :: (store 8)
5252
...
53+
---
54+
name: strxrow_p0
55+
alignment: 4
56+
legalized: true
57+
regBankSelected: true
58+
tracksRegLiveness: true
59+
machineFunctionInfo: {}
60+
body: |
61+
bb.0:
62+
liveins: $x0, $x1, $x2
63+
; CHECK-LABEL: name: strxrow_p0
64+
; CHECK: liveins: $x0, $x1, $x2
65+
; CHECK: %base:gpr64sp = COPY $x0
66+
; CHECK: %foo:gpr32 = COPY $w1
67+
; CHECK: %dst:gpr64all = COPY $x2
68+
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %dst
69+
; CHECK: STRXroW [[COPY]], %base, %foo, 1, 1 :: (store 8)
70+
%base:gpr(p0) = COPY $x0
71+
%foo:gpr(s32) = COPY $w1
72+
%ext:gpr(s64) = G_SEXT %foo(s32)
73+
%c:gpr(s64) = G_CONSTANT i64 3
74+
%offset:gpr(s64) = G_SHL %ext, %c
75+
%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
76+
%dst:gpr(p0) = COPY $x2
77+
G_STORE %dst, %ptr :: (store 8)
78+
...

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