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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4s
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli2d
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_zero_shift_amount
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- ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_trunc_v2i64_v2i8
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- ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_trunc_v4i64_v4i16
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- ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_trunc_v2i64_v2i8
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- ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_trunc_v4i64_v4i16
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- ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_trunc_v4i64_v4i16
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define <8 x i8 > @sqshl8b (ptr %A , ptr %B ) nounwind {
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; CHECK-LABEL: sqshl8b:
@@ -4381,48 +4376,82 @@ define <8 x i16> @signbits_vashr(<8 x i16> %a) {
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}
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define <2 x i8 > @lshr_trunc_v2i64_v2i8 (<2 x i64 > %a ) {
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- ; CHECK-LABEL: lshr_trunc_v2i64_v2i8:
4385
- ; CHECK: // %bb.0:
4386
- ; CHECK-NEXT: shrn v0.2s, v0.2d, #16
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- ; CHECK-NEXT: ret
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+ ; CHECK-SD-LABEL: lshr_trunc_v2i64_v2i8:
4380
+ ; CHECK-SD: // %bb.0:
4381
+ ; CHECK-SD-NEXT: shrn v0.2s, v0.2d, #16
4382
+ ; CHECK-SD-NEXT: ret
4383
+ ;
4384
+ ; CHECK-GI-LABEL: lshr_trunc_v2i64_v2i8:
4385
+ ; CHECK-GI: // %bb.0:
4386
+ ; CHECK-GI-NEXT: xtn v0.2s, v0.2d
4387
+ ; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #16
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+ ; CHECK-GI-NEXT: ret
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%b = lshr <2 x i64 > %a , <i64 16 , i64 16 >
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%c = trunc <2 x i64 > %b to <2 x i8 >
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ret <2 x i8 > %c
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}
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define <4 x i16 > @lshr_trunc_v4i64_v4i16 (<4 x i64 > %a ) {
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- ; CHECK-LABEL: lshr_trunc_v4i64_v4i16:
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- ; CHECK: // %bb.0:
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- ; CHECK-NEXT: xtn v1.2s, v1.2d
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- ; CHECK-NEXT: xtn v0.2s, v0.2d
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- ; CHECK-NEXT: ushr v1.2s, v1.2s, #8
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- ; CHECK-NEXT: ushr v0.2s, v0.2s, #8
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- ; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
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- ; CHECK-NEXT: ret
4395
+ ; CHECK-SD-LABEL: lshr_trunc_v4i64_v4i16:
4396
+ ; CHECK-SD: // %bb.0:
4397
+ ; CHECK-SD-NEXT: xtn v1.2s, v1.2d
4398
+ ; CHECK-SD-NEXT: xtn v0.2s, v0.2d
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+ ; CHECK-SD-NEXT: ushr v1.2s, v1.2s, #8
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+ ; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #8
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+ ; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
4402
+ ; CHECK-SD-NEXT: ret
4403
+ ;
4404
+ ; CHECK-GI-LABEL: lshr_trunc_v4i64_v4i16:
4405
+ ; CHECK-GI: // %bb.0:
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+ ; CHECK-GI-NEXT: adrp x8, .LCPI270_0
4407
+ ; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
4408
+ ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI270_0]
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+ ; CHECK-GI-NEXT: uzp1 v2.4s, v2.4s, v2.4s
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+ ; CHECK-GI-NEXT: neg v1.4s, v2.4s
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+ ; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v1.4s
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+ ; CHECK-GI-NEXT: xtn v0.4h, v0.4s
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+ ; CHECK-GI-NEXT: ret
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%b = lshr <4 x i64 > %a , <i64 8 , i64 8 , i64 8 , i64 8 >
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%c = trunc <4 x i64 > %b to <4 x i16 >
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ret <4 x i16 > %c
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}
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define <2 x i8 > @ashr_trunc_v2i64_v2i8 (<2 x i64 > %a ) {
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- ; CHECK-LABEL: ashr_trunc_v2i64_v2i8:
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- ; CHECK: // %bb.0:
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- ; CHECK-NEXT: shrn v0.2s, v0.2d, #16
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- ; CHECK-NEXT: ret
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+ ; CHECK-SD-LABEL: ashr_trunc_v2i64_v2i8:
4421
+ ; CHECK-SD: // %bb.0:
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+ ; CHECK-SD-NEXT: shrn v0.2s, v0.2d, #16
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+ ; CHECK-SD-NEXT: ret
4424
+ ;
4425
+ ; CHECK-GI-LABEL: ashr_trunc_v2i64_v2i8:
4426
+ ; CHECK-GI: // %bb.0:
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+ ; CHECK-GI-NEXT: xtn v0.2s, v0.2d
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+ ; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
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+ ; CHECK-GI-NEXT: ret
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%b = ashr <2 x i64 > %a , <i64 16 , i64 16 >
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%c = trunc <2 x i64 > %b to <2 x i8 >
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ret <2 x i8 > %c
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}
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define <4 x i16 > @ashr_trunc_v4i64_v4i16 (<4 x i64 > %a ) {
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- ; CHECK-LABEL: ashr_trunc_v4i64_v4i16:
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- ; CHECK: // %bb.0:
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- ; CHECK-NEXT: xtn v1.2s, v1.2d
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- ; CHECK-NEXT: xtn v0.2s, v0.2d
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- ; CHECK-NEXT: ushr v1.2s, v1.2s, #8
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- ; CHECK-NEXT: ushr v0.2s, v0.2s, #8
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- ; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
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- ; CHECK-NEXT: ret
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+ ; CHECK-SD-LABEL: ashr_trunc_v4i64_v4i16:
4437
+ ; CHECK-SD: // %bb.0:
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+ ; CHECK-SD-NEXT: xtn v1.2s, v1.2d
4439
+ ; CHECK-SD-NEXT: xtn v0.2s, v0.2d
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+ ; CHECK-SD-NEXT: ushr v1.2s, v1.2s, #8
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+ ; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #8
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+ ; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
4443
+ ; CHECK-SD-NEXT: ret
4444
+ ;
4445
+ ; CHECK-GI-LABEL: ashr_trunc_v4i64_v4i16:
4446
+ ; CHECK-GI: // %bb.0:
4447
+ ; CHECK-GI-NEXT: adrp x8, .LCPI272_0
4448
+ ; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
4449
+ ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI272_0]
4450
+ ; CHECK-GI-NEXT: uzp1 v2.4s, v2.4s, v2.4s
4451
+ ; CHECK-GI-NEXT: neg v1.4s, v2.4s
4452
+ ; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s
4453
+ ; CHECK-GI-NEXT: xtn v0.4h, v0.4s
4454
+ ; CHECK-GI-NEXT: ret
4426
4455
%b = ashr <4 x i64 > %a , <i64 8 , i64 8 , i64 8 , i64 8 >
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%c = trunc <4 x i64 > %b to <4 x i16 >
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ret <4 x i16 > %c
@@ -4446,12 +4475,23 @@ define <2 x i8> @shl_trunc_v2i64_v2i8(<2 x i64> %a) {
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}
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define <4 x i16 > @shl_trunc_v4i64_v4i16 (<4 x i64 > %a ) {
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- ; CHECK-LABEL: shl_trunc_v4i64_v4i16:
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- ; CHECK: // %bb.0:
4451
- ; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s
4452
- ; CHECK-NEXT: xtn v0.4h, v0.4s
4453
- ; CHECK-NEXT: shl v0.4h, v0.4h, #8
4454
- ; CHECK-NEXT: ret
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+ ; CHECK-SD-LABEL: shl_trunc_v4i64_v4i16:
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+ ; CHECK-SD: // %bb.0:
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+ ; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s
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+ ; CHECK-SD-NEXT: xtn v0.4h, v0.4s
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+ ; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
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+ ; CHECK-SD-NEXT: ret
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+ ;
4485
+ ; CHECK-GI-LABEL: shl_trunc_v4i64_v4i16:
4486
+ ; CHECK-GI: // %bb.0:
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+ ; CHECK-GI-NEXT: adrp x8, .LCPI274_0
4488
+ ; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
4489
+ ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI274_0]
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+ ; CHECK-GI-NEXT: uzp1 v1.4s, v2.4s, v2.4s
4491
+ ; CHECK-GI-NEXT: xtn v0.4h, v0.4s
4492
+ ; CHECK-GI-NEXT: xtn v1.4h, v1.4s
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+ ; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v1.4h
4494
+ ; CHECK-GI-NEXT: ret
4455
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%b = shl <4 x i64 > %a , <i64 8 , i64 8 , i64 8 , i64 8 >
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%c = trunc <4 x i64 > %b to <4 x i16 >
4457
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ret <4 x i16 > %c
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