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AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands.
We would still need to waterfall if the value were somehow an AGPR, and also need to explicitly copy to a VGPR.
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3 files changed

+213
-12
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3 files changed

+213
-12
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp‎

Lines changed: 29 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -847,7 +847,18 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
847847
continue;
848848
}
849849

850-
LLT OpTy = MRI.getType(Op.getReg());
850+
Register OpReg = Op.getReg();
851+
LLT OpTy = MRI.getType(OpReg);
852+
853+
const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI);
854+
if (OpBank != &AMDGPU::VGPRRegBank) {
855+
// Insert copy from AGPR to VGPR before the loop.
856+
B.setMBB(MBB);
857+
OpReg = B.buildCopy(OpTy, OpReg).getReg(0);
858+
MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank);
859+
B.setInstr(*I);
860+
}
861+
851862
unsigned OpSize = OpTy.getSizeInBits();
852863

853864
// Can only do a readlane of 32-bit pieces.
@@ -857,11 +868,11 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
857868
= MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
858869
MRI.setType(CurrentLaneOpReg, OpTy);
859870

860-
constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
871+
constrainGenericRegister(OpReg, AMDGPU::VGPR_32RegClass, MRI);
861872
// Read the next variant <- also loop target.
862873
BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
863874
CurrentLaneOpReg)
864-
.addReg(Op.getReg());
875+
.addReg(OpReg);
865876

866877
Register NewCondReg = MRI.createVirtualRegister(WaveRC);
867878
bool First = CondReg == AMDGPU::NoRegister;
@@ -872,7 +883,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
872883
B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64)
873884
.addDef(NewCondReg)
874885
.addReg(CurrentLaneOpReg)
875-
.addReg(Op.getReg());
886+
.addReg(OpReg);
876887
Op.setReg(CurrentLaneOpReg);
877888

878889
if (!First) {
@@ -904,7 +915,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
904915
// Insert the unmerge before the loop.
905916

906917
B.setMBB(MBB);
907-
auto Unmerge = B.buildUnmerge(UnmergeTy, Op.getReg());
918+
auto Unmerge = B.buildUnmerge(UnmergeTy, OpReg);
908919
B.setInstr(*I);
909920

910921
unsigned NumPieces = Unmerge->getNumOperands() - 1;
@@ -1048,7 +1059,7 @@ bool AMDGPURegisterBankInfo::collectWaterfallOperands(
10481059
assert(MI.getOperand(Op).isUse());
10491060
Register Reg = MI.getOperand(Op).getReg();
10501061
const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI);
1051-
if (OpBank->getID() == AMDGPU::VGPRRegBankID)
1062+
if (OpBank->getID() != AMDGPU::SGPRRegBankID)
10521063
SGPROperandRegs.insert(Reg);
10531064
}
10541065

@@ -1083,16 +1094,24 @@ void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(
10831094
MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const {
10841095
Register Reg = MI.getOperand(OpIdx).getReg();
10851096
const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
1086-
if (Bank != &AMDGPU::VGPRRegBank)
1097+
if (Bank == &AMDGPU::SGPRRegBank)
10871098
return;
10881099

1100+
LLT Ty = MRI.getType(Reg);
10891101
MachineIRBuilder B(MI);
1102+
1103+
if (Bank != &AMDGPU::VGPRRegBank) {
1104+
// We need to copy from AGPR to VGPR
1105+
Reg = B.buildCopy(Ty, Reg).getReg(0);
1106+
MRI.setRegBank(Reg, AMDGPU::VGPRRegBank);
1107+
}
1108+
10901109
Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
10911110
B.buildInstr(AMDGPU::V_READFIRSTLANE_B32)
10921111
.addDef(SGPR)
10931112
.addReg(Reg);
10941113

1095-
MRI.setType(SGPR, MRI.getType(Reg));
1114+
MRI.setType(SGPR, Ty);
10961115

10971116
const TargetRegisterClass *Constrained =
10981117
constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI);
@@ -1922,7 +1941,7 @@ bool AMDGPURegisterBankInfo::foldExtractEltToCmpSelect(
19221941
const RegisterBank &IdxBank =
19231942
*OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
19241943

1925-
bool IsDivergentIdx = IdxBank == AMDGPU::VGPRRegBank;
1944+
bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank;
19261945

19271946
LLT VecTy = MRI.getType(VecReg);
19281947
unsigned EltSize = VecTy.getScalarSizeInBits();
@@ -2004,7 +2023,7 @@ bool AMDGPURegisterBankInfo::foldInsertEltToCmpSelect(
20042023
const RegisterBank &IdxBank =
20052024
*OpdMapper.getInstrMapping().getOperandMapping(3).BreakDown[0].RegBank;
20062025

2007-
bool IsDivergentIdx = IdxBank == AMDGPU::VGPRRegBank;
2026+
bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank;
20082027

20092028
LLT VecTy = MRI.getType(VecReg);
20102029
unsigned EltSize = VecTy.getScalarSizeInBits();

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir‎

Lines changed: 77 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3-
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
2+
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3+
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
44

55
---
66
name: readlane_ss
@@ -69,3 +69,78 @@ body: |
6969
%1:_(s32) = COPY $vgpr0
7070
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
7171
...
72+
73+
---
74+
name: readlane_aa
75+
legalized: true
76+
77+
body: |
78+
bb.0:
79+
liveins: $agpr0, $agpr1
80+
; CHECK-LABEL: name: readlane_aa
81+
; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
82+
; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
83+
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
84+
; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
85+
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
86+
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
87+
; CHECK: S_ENDPGM 0, implicit [[INT]](s32)
88+
%0:_(s32) = COPY $agpr0
89+
%1:_(s32) = COPY $agpr1
90+
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
91+
S_ENDPGM 0, implicit %2
92+
...
93+
94+
---
95+
name: readlane_as
96+
legalized: true
97+
98+
body: |
99+
bb.0:
100+
liveins: $agpr0, $sgpr0
101+
; CHECK-LABEL: name: readlane_as
102+
; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
103+
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
104+
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
105+
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)
106+
%0:_(s32) = COPY $agpr0
107+
%1:_(s32) = COPY $sgpr0
108+
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
109+
...
110+
111+
---
112+
name: readlane_sa
113+
legalized: true
114+
115+
body: |
116+
bb.0:
117+
liveins: $agpr0, $sgpr0
118+
; CHECK-LABEL: name: readlane_sa
119+
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
120+
; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
121+
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
122+
; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
123+
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
124+
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
125+
%0:_(s32) = COPY $sgpr0
126+
%1:_(s32) = COPY $agpr0
127+
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
128+
...
129+
130+
---
131+
name: readlane_va
132+
legalized: true
133+
134+
body: |
135+
bb.0:
136+
liveins: $vgpr0, $agpr0
137+
; CHECK-LABEL: name: readlane_va
138+
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
139+
; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
140+
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
141+
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY2]](s32), implicit $exec
142+
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)
143+
%0:_(s32) = COPY $vgpr0
144+
%1:_(s32) = COPY $agpr0
145+
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
146+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir‎

Lines changed: 107 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,107 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=regbankselect -o - %s | FileCheck %s
3+
4+
# Make sure that an arbitrary AGPR is treated as a divergent value
5+
# that needs to be copied to VGPR, and then waterfalled
6+
7+
# 32-bit case
8+
---
9+
name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__agpr_soffset
10+
legalized: true
11+
tracksRegLiveness: true
12+
body: |
13+
bb.0:
14+
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0, $vgpr1, $agpr0
15+
16+
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__agpr_soffset
17+
; CHECK: successors: %bb.1(0x80000000)
18+
; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0, $vgpr1, $agpr0
19+
; CHECK: %val:vgpr(s32) = COPY $vgpr0
20+
; CHECK: %rsrc:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
21+
; CHECK: %agpr:agpr(s32) = COPY $agpr0
22+
; CHECK: %voffset:vgpr(s32) = COPY $vgpr1
23+
; CHECK: %zero:sgpr(s32) = G_CONSTANT i32 0
24+
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY %zero(s32)
25+
; CHECK: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
26+
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY %agpr(s32)
27+
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
28+
; CHECK: .1:
29+
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
30+
; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.0, %9, %bb.1
31+
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
32+
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
33+
; CHECK: G_AMDGPU_BUFFER_STORE %val(s32), %rsrc(<4 x s32>), [[COPY]](s32), %voffset, [[V_READFIRSTLANE_B32_]], 0, 0, 0 :: (dereferenceable store 4, addrspace 4)
34+
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
35+
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
36+
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
37+
; CHECK: .2:
38+
; CHECK: successors: %bb.3(0x80000000)
39+
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
40+
; CHECK: .3:
41+
; CHECK: S_ENDPGM 0
42+
%val:_(s32) = COPY $vgpr0
43+
%rsrc:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
44+
%agpr:_(s32) = COPY $agpr0
45+
%voffset:_(s32) = COPY $vgpr1
46+
%zero:_(s32) = G_CONSTANT i32 0
47+
G_AMDGPU_BUFFER_STORE %val, %rsrc, %zero, %voffset, %agpr, 0, 0, 0 :: (dereferenceable store 4, addrspace 4)
48+
S_ENDPGM 0
49+
50+
...
51+
52+
# Register tuple case
53+
---
54+
name: load_1d_vgpr_vaddr__agpr_srsrc
55+
legalized: true
56+
tracksRegLiveness: true
57+
body: |
58+
bb.0:
59+
liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, $vgpr0
60+
; CHECK-LABEL: name: load_1d_vgpr_vaddr__agpr_srsrc
61+
; CHECK: successors: %bb.1(0x80000000)
62+
; CHECK: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, $vgpr0
63+
; CHECK: [[COPY:%[0-9]+]]:agpr(<8 x s32>) = COPY $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
64+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
65+
; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
66+
; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
67+
; CHECK: [[COPY2:%[0-9]+]]:vgpr(<8 x s32>) = COPY [[COPY]](<8 x s32>)
68+
; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY2]](<8 x s32>)
69+
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
70+
; CHECK: .1:
71+
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
72+
; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.0, %8, %bb.1
73+
; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1
74+
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec
75+
; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec
76+
; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
77+
; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
78+
; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub0(s64), implicit $exec
79+
; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub1(s64), implicit $exec
80+
; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
81+
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
82+
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
83+
; CHECK: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]].sub0(s64), implicit $exec
84+
; CHECK: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]].sub1(s64), implicit $exec
85+
; CHECK: [[MV2:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32)
86+
; CHECK: [[V_CMP_EQ_U64_e64_2:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV2]](s64), [[UV2]](s64), implicit $exec
87+
; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_2]], [[S_AND_B64_]], implicit-def $scc
88+
; CHECK: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]].sub0(s64), implicit $exec
89+
; CHECK: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]].sub1(s64), implicit $exec
90+
; CHECK: [[MV3:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
91+
; CHECK: [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV3]](s64), [[UV3]](s64), implicit $exec
92+
; CHECK: [[S_AND_B64_2:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_3]], [[S_AND_B64_1]], implicit-def $scc
93+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32), [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32), [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
94+
; CHECK: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY1]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16)
95+
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_2]], implicit-def $exec, implicit-def $scc, implicit $exec
96+
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
97+
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
98+
; CHECK: .2:
99+
; CHECK: successors: %bb.3(0x80000000)
100+
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
101+
; CHECK: .3:
102+
; CHECK: S_ENDPGM 0, implicit [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
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%0:_(<8 x s32>) = COPY $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
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%1:_(s32) = COPY $vgpr0
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%2:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, %1(s32), %0(<8 x s32>), 0, 0, 0 :: (dereferenceable load 16)
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S_ENDPGM 0, implicit %2
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...

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