[DAGCombine] Fix an ICE in combineMinNumMaxNum(...)

65420c8 introduced an ICE in combineMinNumMaxNum(...) when
combineMinNumMaxNumImpl(...) returns an SDValue(). Make sure to check that a
value is returned before trying to perform an FNEG on it.

GitHub Issue: #60924

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D144571

(cherry picked from commit af4c4f4)

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -10447,7 +10447,8 @@ SDValue DAGCombiner::combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
       if (NegRHS == False) {
         SDValue Combined = combineMinNumMaxNumImpl(DL, VT, LHS, RHS, NegTrue,
                                                    False, CC, TLI, DAG);
-        return DAG.getNode(ISD::FNEG, DL, VT, Combined);
+        if (Combined)
+          return DAG.getNode(ISD::FNEG, DL, VT, Combined);
       }
     }
   }

llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll

@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake
+
+; Checking for a DAGCombine ICE.
+
+define float @test_combinemaxnum(float %sub) #0 {
+L.entry:
+  %maxnum1 = call float @llvm.maxnum.f32(float 0.000000e+00, float 0.000000e+00)
+  br label %L.LB21_850
+
+L.LB21_850:
+  %neg1 = fneg fast float %maxnum1
+  %neg2 = fneg fast float %sub
+  %mask = fcmp fast ule float %maxnum1, %neg2
+  %maxnum2 = select i1 %mask, float %neg1, float %sub
+  ret float %maxnum2
+}
+
+declare float @llvm.maxnum.f32(float, float) 
+
+attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }