[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0

Add unordered indexed load: vluxei Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D95028
llvm · Jan 22, 2021 · 976cf53 · 976cf53
1 parent bea661d
commit 976cf53
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Showing 4 changed files with 10,045 additions and 3 deletions.
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -710,9 +710,10 @@ let TargetPrefix = "riscv" in {
   defm vse : RISCVUSStore;
   defm vlse: RISCVSLoad;
   defm vsse: RISCVSStore;
-  defm vloxei: RISCVILoad;
-  defm vsoxei: RISCVIStore;
-  defm vsuxei: RISCVIStore;
+  defm vluxei : RISCVILoad;
+  defm vloxei : RISCVILoad;
+  defm vsoxei : RISCVIStore;
+  defm vsuxei : RISCVIStore;
 
   defm vamoswap : RISCVAMO;
   defm vamoadd : RISCVAMO;

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2944,6 +2944,7 @@ foreach eew = EEWList in {
 
 // Vector Indexed Loads and Stores
 foreach eew = EEWList in {
+  defm PseudoVLUXEI # eew : VPseudoILoad;
   defm PseudoVLOXEI # eew : VPseudoILoad;
   defm PseudoVSOXEI # eew : VPseudoIStore;
   defm PseudoVSUXEI # eew : VPseudoIStore;
@@ -3517,6 +3518,10 @@ foreach eew = EEWList in {
        defvar elmul =!cast<LMULInfo>("V_" # elmul_str);
        defvar idx_vti = !cast<VTypeInfo>("VI" # eew # elmul_str);
 
+       defm : VPatILoad<"int_riscv_vluxei",
+                        "PseudoVLUXEI"#eew,
+                         vti.Vector, idx_vti.Vector, vti.Mask, vti.SEW,
+                         vlmul, elmul, vti.RegClass, idx_vti.RegClass>;
        defm : VPatILoad<"int_riscv_vloxei",
                         "PseudoVLOXEI"#eew,
                          vti.Vector, idx_vti.Vector, vti.Mask, vti.SEW,