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‎llvm/test/Transforms/LoopVectorize/AArch64/sve-predicated-costs.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -mtriple=aarch64 -mattr=+sve -S %s | FileCheck %s
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define void @nested(ptr noalias %p0, ptr noalias %p1, i1 %c0, i1 %c1) {
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; CHECK-LABEL: define void @nested(
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; CHECK-SAME: ptr noalias [[P0:%.*]], ptr noalias [[P1:%.*]], i1 [[C0:%.*]], i1 [[C1:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 [[TMP0]], 2
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 1024, [[TMP1]]
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP2]], 4
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 1024, [[TMP3]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 1024, [[N_MOD_VF]]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i1> poison, i1 [[C1]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i1> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i1> poison, i1 [[C0]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i1> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = select <vscale x 2 x i1> [[BROADCAST_SPLAT2]], <vscale x 2 x i1> [[BROADCAST_SPLAT]], <vscale x 2 x i1> zeroinitializer
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[P0]], i32 [[IV1]]
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; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP7:%.*]] = shl nuw i64 [[TMP6]], 1
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP5]], i64 [[TMP7]]
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; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP5]], i32 8, <vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[WIDE_MASKED_LOAD3:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP8]], i32 8, <vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[P1]], i32 [[IV1]]
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; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 1
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, ptr [[TMP9]], i64 [[TMP11]]
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; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP9]], i32 8, <vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP12]], i32 8, <vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[TMP13:%.*]] = select <vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> [[WIDE_MASKED_LOAD4]], <vscale x 2 x i64> splat (i64 1)
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; CHECK-NEXT: [[TMP14:%.*]] = select <vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> [[WIDE_MASKED_LOAD5]], <vscale x 2 x i64> splat (i64 1)
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; CHECK-NEXT: [[TMP15:%.*]] = udiv <vscale x 2 x i64> [[WIDE_MASKED_LOAD]], [[TMP13]]
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; CHECK-NEXT: [[TMP16:%.*]] = udiv <vscale x 2 x i64> [[WIDE_MASKED_LOAD3]], [[TMP14]]
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; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP18:%.*]] = shl nuw i64 [[TMP17]], 1
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[TMP9]], i64 [[TMP18]]
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; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP15]], ptr [[TMP9]], i32 8, <vscale x 2 x i1> [[TMP4]])
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; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP16]], ptr [[TMP19]], i32 8, <vscale x 2 x i1> [[TMP4]])
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[IV1]], [[TMP3]]
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; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 1024, [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[X:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
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; CHECK-NEXT: br i1 [[C0]], label %[[THEN_0:.*]], label %[[LATCH]]
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; CHECK: [[THEN_0]]:
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; CHECK-NEXT: br i1 [[C1]], label %[[THEN_1:.*]], label %[[LATCH]]
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; CHECK: [[THEN_1]]:
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; CHECK-NEXT: [[GEP0:%.*]] = getelementptr i64, ptr [[P0]], i32 [[X]]
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; CHECK-NEXT: [[X1:%.*]] = load i64, ptr [[GEP0]], align 8
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; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[P1]], i32 [[X]]
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; CHECK-NEXT: [[Y:%.*]] = load i64, ptr [[GEP1]], align 8
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; CHECK-NEXT: [[Z:%.*]] = udiv i64 [[X1]], [[Y]]
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; CHECK-NEXT: store i64 [[Z]], ptr [[GEP1]], align 8
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; CHECK-NEXT: br label %[[LATCH]]
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; CHECK: [[LATCH]]:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[X]], 1
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT]], 1024
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; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ]
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br i1 %c0, label %then.0, label %latch
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then.0:
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br i1 %c1, label %then.1, label %latch
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then.1:
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%gep0 = getelementptr i64, ptr %p0, i32 %iv
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%x = load i64, ptr %gep0
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%gep1 = getelementptr i64, ptr %p1, i32 %iv
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%y = load i64, ptr %gep1
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%z = udiv i64 %x, %y
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store i64 %z, ptr %gep1
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br label %latch
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latch:
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%iv.next = add i32 %iv, 1
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%done = icmp eq i32 %iv.next, 1024
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br i1 %done, label %exit, label %loop
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exit:
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ret void
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}
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define void @always_taken(ptr noalias %p0, ptr noalias %p1, i1 %c0, i1 %c1) {
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; CHECK-LABEL: define void @always_taken(
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; CHECK-SAME: ptr noalias [[P0:%.*]], ptr noalias [[P1:%.*]], i1 [[C0:%.*]], i1 [[C1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 [[TMP0]], 2
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 1024, [[TMP1]]
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP4]], 4
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 1024, [[TMP5]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 1024, [[N_MOD_VF]]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i1> poison, i1 [[C1]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i1> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i1> poison, i1 [[C0]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i1> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = select <vscale x 2 x i1> [[BROADCAST_SPLAT2]], <vscale x 2 x i1> [[BROADCAST_SPLAT]], <vscale x 2 x i1> zeroinitializer
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[P0]], i32 [[INDEX]]
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; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP7:%.*]] = shl nuw i64 [[TMP8]], 1
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; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i64, ptr [[TMP10]], i64 [[TMP7]]
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; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP10]], i32 8, <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[WIDE_MASKED_LOAD3:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP20]], i32 8, <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[P1]], i32 [[INDEX]]
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; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP13]], 1
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, ptr [[TMP9]], i64 [[TMP11]]
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; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP9]], i32 8, <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP12]], i32 8, <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i64> poison)
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; CHECK-NEXT: [[TMP21:%.*]] = select <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i64> [[WIDE_MASKED_LOAD4]], <vscale x 2 x i64> splat (i64 1)
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; CHECK-NEXT: [[TMP14:%.*]] = select <vscale x 2 x i1> [[TMP6]], <vscale x 2 x i64> [[WIDE_MASKED_LOAD5]], <vscale x 2 x i64> splat (i64 1)
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; CHECK-NEXT: [[TMP15:%.*]] = udiv <vscale x 2 x i64> [[WIDE_MASKED_LOAD]], [[TMP21]]
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; CHECK-NEXT: [[TMP22:%.*]] = udiv <vscale x 2 x i64> [[WIDE_MASKED_LOAD3]], [[TMP14]]
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; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP18:%.*]] = shl nuw i64 [[TMP17]], 1
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[TMP9]], i64 [[TMP18]]
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; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP15]], ptr [[TMP9]], i32 8, <vscale x 2 x i1> [[TMP6]])
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; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP22]], ptr [[TMP19]], i32 8, <vscale x 2 x i1> [[TMP6]])
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP5]]
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; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 1024, [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], %[[LATCH:.*]] ]
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; CHECK-NEXT: br i1 [[C0]], label %[[THEN_0:.*]], label %[[LATCH]], !prof [[PROF5:![0-9]+]]
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; CHECK: [[THEN_0]]:
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; CHECK-NEXT: br i1 [[C1]], label %[[THEN_1:.*]], label %[[LATCH]], !prof [[PROF5]]
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; CHECK: [[THEN_1]]:
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; CHECK-NEXT: [[GEP0:%.*]] = getelementptr i64, ptr [[P0]], i32 [[IV1]]
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; CHECK-NEXT: [[X:%.*]] = load i64, ptr [[GEP0]], align 8
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; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, ptr [[P1]], i32 [[IV1]]
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; CHECK-NEXT: [[Y:%.*]] = load i64, ptr [[GEP1]], align 8
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; CHECK-NEXT: [[Z:%.*]] = udiv i64 [[X]], [[Y]]
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; CHECK-NEXT: store i64 [[Z]], ptr [[GEP1]], align 8
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; CHECK-NEXT: br label %[[LATCH]]
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; CHECK: [[LATCH]]:
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; CHECK-NEXT: [[IV_NEXT1]] = add i32 [[IV1]], 1
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT1]], 1024
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; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ]
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br i1 %c0, label %then.0, label %latch, !prof !4
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then.0:
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br i1 %c1, label %then.1, label %latch, !prof !4
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then.1:
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%gep0 = getelementptr i64, ptr %p0, i32 %iv
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%x = load i64, ptr %gep0
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%gep1 = getelementptr i64, ptr %p1, i32 %iv
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%y = load i64, ptr %gep1
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%z = udiv i64 %x, %y
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store i64 %z, ptr %gep1
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br label %latch
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latch:
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%iv.next = add i32 %iv, 1
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%done = icmp eq i32 %iv.next, 1024
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br i1 %done, label %exit, label %loop
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exit:
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ret void
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}
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!4 = !{!"branch_weights", i32 1, i32 0}
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