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SystemZ: Implement copyPhysReg between vr128 and gr128
I have no idea if this is correct and I probably swapped the element ordering somewhere.
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‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -840,6 +840,41 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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return;
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}
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if (SystemZ::GR128BitRegClass.contains(DestReg) &&
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SystemZ::VR128BitRegClass.contains(SrcReg)) {
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MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64);
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MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64);
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BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestL64)
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.addReg(SrcReg)
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.addReg(SystemZ::NoRegister)
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.addImm(0)
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.addDef(DestReg, RegState::Implicit);
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BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestH64)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(SystemZ::NoRegister)
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.addImm(1);
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return;
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}
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if (SystemZ::VR128BitRegClass.contains(DestReg) &&
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SystemZ::GR128BitRegClass.contains(SrcReg)) {
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MCRegister SrcH64 = RI.getSubReg(SrcReg, SystemZ::subreg_h64);
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MCRegister SrcL64 = RI.getSubReg(SrcReg, SystemZ::subreg_l64);
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BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGG), DestReg)
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.addReg(DestReg, RegState::Undef)
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.addReg(SrcH64)
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.addReg(SystemZ::NoRegister)
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.addImm(0);
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BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGG), DestReg)
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.addReg(DestReg)
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.addReg(SrcL64)
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.addReg(SystemZ::NoRegister)
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.addImm(1);
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return;
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}
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// Everything else needs only one instruction.
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unsigned Opcode;
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if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))

‎llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir‎

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
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---
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name: copy_gr128_to_vr128__r0q_to_v0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0
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; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1
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; CHECK-NEXT: Return implicit $v0
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$v0 = COPY $r0q
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Return implicit $v0
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...
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---
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name: copy_gr128_to_vr128__r0q_to_v0_killed
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_killed
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0
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; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1
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; CHECK-NEXT: Return implicit $v0
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$v0 = COPY killed $r0q
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Return implicit $v0
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...
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---
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name: copy_gr128_to_vr128__r0q_to_v0_undef
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_undef
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $v0 = KILL undef $r0q
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; CHECK-NEXT: Return implicit $v0
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$v0 = COPY undef $r0q
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Return implicit $v0
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...
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---
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name: copy_gr128_to_vr128__r0q_to_v0_subreg0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0d
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; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg0
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; CHECK: liveins: $r0d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0
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; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1
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; CHECK-NEXT: Return implicit $v0
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$v0 = COPY $r0q
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Return implicit $v0
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...
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---
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name: copy_gr128_to_vr128__r0q_to_v0_subreg1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r1d
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; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg1
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; CHECK: liveins: $r1d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0
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; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1
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; CHECK-NEXT: Return implicit $v0
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$v0 = COPY $r0q
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Return implicit $v0
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...
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‎llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
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---
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name: copy_vr128_to_gr128__v0_to_r0q
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $v0
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; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q
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; CHECK: liveins: $v0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 0, implicit-def $r0q
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; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 1
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; CHECK-NEXT: Return implicit $r0q
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$r0q = COPY $v0
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Return implicit $r0q
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...
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---
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name: copy_vr128_to_gr128__v0_to_r0q_killed
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $v0
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; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_killed
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; CHECK: liveins: $v0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 0, implicit-def $r0q
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; CHECK-NEXT: $r0d = VLGVG killed $v0, $noreg, 1
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; CHECK-NEXT: Return implicit $r0q
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$r0q = COPY killed $v0
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Return implicit $r0q
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...
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---
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name: copy_vr128_to_gr128__v0_to_r0q_undef
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef
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; CHECK: $r0q = KILL undef $v0
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; CHECK-NEXT: Return implicit $r0q
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$r0q = COPY undef $v0
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Return implicit $r0q
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...
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---
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name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg0
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg0
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; CHECK: $r0q = KILL undef $v0
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; CHECK-NEXT: Return implicit $r0d
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$r0q = COPY undef $v0
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Return implicit $r0d
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...
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---
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name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg1
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg1
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; CHECK: $r0q = KILL undef $v0
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; CHECK-NEXT: Return implicit $r1d
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$r0q = COPY undef $v0
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Return implicit $r1d
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...

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