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[RISCV] Make LMUL field in VTYPE continuous.
Upgrade RISC-V V extension to v1.0-08a0b46. Update the VTYPE encoding. Make LMUL encoding in a continuous field.
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5 files changed

+37
-42
lines changed

5 files changed

+37
-42
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -353,17 +353,13 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
353353
// -----+------------+------------------------------------------------
354354
// 7 | vma | Vector mask agnostic
355355
// 6 | vta | Vector tail agnostic
356-
// 5 | vlmul[2] | Fractional lmul?
357-
// 4:2 | vsew[2:0] | Standard element width (SEW) setting
358-
// 1:0 | vlmul[1:0] | Vector register group multiplier (LMUL) setting
359-
//
360-
// TODO: This format will change for the V extensions spec v1.0.
356+
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
357+
// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
361358
inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
362359
bool TailAgnostic, bool MaskAgnostic) {
363360
unsigned VLMULBits = static_cast<unsigned>(VLMUL);
364361
unsigned VSEWBits = static_cast<unsigned>(VSEW);
365-
unsigned VTypeI =
366-
((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3);
362+
unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
367363
if (TailAgnostic)
368364
VTypeI |= 0x40;
369365
if (MaskAgnostic)
@@ -372,14 +368,13 @@ inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
372368
return VTypeI;
373369
}
374370

375-
// TODO: This format will change for the V extensions spec v1.0.
376371
inline static RISCVVLMUL getVLMUL(unsigned VType) {
377-
unsigned VLMUL = (VType & 0x3) | ((VType & 0x20) >> 3);
372+
unsigned VLMUL = VType & 0x7;
378373
return static_cast<RISCVVLMUL>(VLMUL);
379374
}
380375

381376
inline static RISCVVSEW getVSEW(unsigned VType) {
382-
unsigned VSEW = (VType >> 2) & 0x7;
377+
unsigned VSEW = (VType >> 3) & 0x7;
383378
return static_cast<RISCVVSEW>(VSEW);
384379
}
385380

‎llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,13 @@ body: |
3939
# POST-INSERTER: %1:gpr = COPY $x12
4040
# POST-INSERTER: %2:gpr = COPY $x11
4141
# POST-INSERTER: %3:gpr = COPY $x10
42-
# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
42+
# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
4343
# POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
44-
# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
44+
# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
4545
# POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
46-
# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
46+
# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
4747
# POST-INSERTER: %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, $noreg, -1, implicit $vl, implicit $vtype
48-
# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
48+
# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
4949
# POST-INSERTER: PseudoVSE64_V_M1 killed %6, %3, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
5050

5151
# CODEGEN: vsetvli a3, a3, e64,m1,ta,mu

‎llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,11 +25,11 @@ define void @vadd_vint64m1(
2525
; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype
2626
; PRE-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
2727

28-
; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
28+
; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
2929
; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
30-
; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
30+
; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
3131
; POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
32-
; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
32+
; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
3333
; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype
34-
; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
34+
; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
3535
; POST-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)

‎llvm/test/MC/RISCV/rvv/snippet.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66

77
loop:
88
vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors
9-
# CHECK-INST: d7 76 65 0c vsetvli a3, a0, e16,m4,ta,ma
9+
# CHECK-INST: d7 76 a5 0c vsetvli a3, a0, e16,m4,ta,ma
1010
vle16.v v4, (a1) # Get 16b vector
1111
# CHECK-INST: 07 d2 05 02 vle16.v v4, (a1)
1212
slli t1, a3, 1 # Multiply length by two bytes/element
@@ -17,7 +17,7 @@ loop:
1717
# CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0
1818

1919
vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values
20-
# CHECK-INST: 57 70 b5 0c vsetvli zero, a0, e32,m8,ta,ma
20+
# CHECK-INST: 57 70 35 0d vsetvli zero, a0, e32,m8,ta,ma
2121
vsrl.vi v8, v8, 3
2222
# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3
2323
vse32.v v8, (a2) # Store vector of 32b

‎llvm/test/MC/RISCV/rvv/vsetvl.s

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -10,69 +10,69 @@
1010

1111
vsetvli a2, a0, e32,m1,ta,ma
1212
# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
13-
# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
13+
# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
1414
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
15-
# CHECK-UNKNOWN: 57 76 85 0c <unknown>
15+
# CHECK-UNKNOWN: 57 76 05 0d <unknown>
1616

1717
vsetvli a2, a0, e32,m2,ta,ma
1818
# CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma
19-
# CHECK-ENCODING: [0x57,0x76,0x95,0x0c]
19+
# CHECK-ENCODING: [0x57,0x76,0x15,0x0d]
2020
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
21-
# CHECK-UNKNOWN: 57 76 95 0c <unknown>
21+
# CHECK-UNKNOWN: 57 76 15 0d <unknown>
2222

2323
vsetvli a2, a0, e32,m4,ta,ma
2424
# CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma
25-
# CHECK-ENCODING: [0x57,0x76,0xa5,0x0c]
25+
# CHECK-ENCODING: [0x57,0x76,0x25,0x0d]
2626
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
27-
# CHECK-UNKNOWN: 57 76 a5 0c <unknown>
27+
# CHECK-UNKNOWN: 57 76 25 0d <unknown>
2828

2929
vsetvli a2, a0, e32,m8,ta,ma
3030
# CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma
31-
# CHECK-ENCODING: [0x57,0x76,0xb5,0x0c]
31+
# CHECK-ENCODING: [0x57,0x76,0x35,0x0d]
3232
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
33-
# CHECK-UNKNOWN: 57 76 b5 0c <unknown>
33+
# CHECK-UNKNOWN: 57 76 35 0d <unknown>
3434

3535
vsetvli a2, a0, e32,mf2,ta,ma
3636
# CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma
37-
# CHECK-ENCODING: [0x57,0x76,0xb5,0x0e]
37+
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
3838
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
39-
# CHECK-UNKNOWN: 57 76 b5 0e <unknown>
39+
# CHECK-UNKNOWN: 57 76 75 0d <unknown>
4040

4141
vsetvli a2, a0, e32,mf4,ta,ma
4242
# CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma
43-
# CHECK-ENCODING: [0x57,0x76,0xa5,0x0e]
43+
# CHECK-ENCODING: [0x57,0x76,0x65,0x0d]
4444
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
45-
# CHECK-UNKNOWN: 57 76 a5 0e <unknown>
45+
# CHECK-UNKNOWN: 57 76 65 0d <unknown>
4646

4747
vsetvli a2, a0, e32,mf8,ta,ma
4848
# CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma
49-
# CHECK-ENCODING: [0x57,0x76,0x95,0x0e]
49+
# CHECK-ENCODING: [0x57,0x76,0x55,0x0d]
5050
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
51-
# CHECK-UNKNOWN: 57 76 95 0e <unknown>
51+
# CHECK-UNKNOWN: 57 76 55 0d <unknown>
5252

5353
vsetvli a2, a0, e32,m1,ta,ma
5454
# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
55-
# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
55+
# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
5656
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
57-
# CHECK-UNKNOWN: 57 76 85 0c <unknown>
57+
# CHECK-UNKNOWN: 57 76 05 0d <unknown>
5858

5959
vsetvli a2, a0, e32,m1,tu,ma
6060
# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
61-
# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
61+
# CHECK-ENCODING: [0x57,0x76,0x05,0x09]
6262
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
63-
# CHECK-UNKNOWN: 57 76 85 08 <unknown>
63+
# CHECK-UNKNOWN: 57 76 05 09 <unknown>
6464

6565
vsetvli a2, a0, e32,m1,ta,mu
6666
# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
67-
# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
67+
# CHECK-ENCODING: [0x57,0x76,0x05,0x05]
6868
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
69-
# CHECK-UNKNOWN: 57 76 85 04 <unknown>
69+
# CHECK-UNKNOWN: 57 76 05 05 <unknown>
7070

7171
vsetvli a2, a0, e32,m1,tu,mu
7272
# CHECK-INST: vsetvli a2, a0, e32,m1
73-
# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
73+
# CHECK-ENCODING: [0x57,0x76,0x05,0x01]
7474
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
75-
# CHECK-UNKNOWN: 57 76 85 00 <unknown>
75+
# CHECK-UNKNOWN: 57 76 05 01 <unknown>
7676

7777
vsetvl a2, a0, a1
7878
# CHECK-INST: vsetvl a2, a0, a1

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