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[RISCV] Update computeKnownBitsForTargetNode for FPCLASS.
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The fclass instruction only set one of the low 10 bits.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154040
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jacquesguan committed Jun 29, 2023
1 parent d2640f5 commit a09a19b
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Showing 2 changed files with 9 additions and 8 deletions.
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -13147,6 +13147,11 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known.One.setBit(Log2_32(MinVLenB));
break;
}
case RISCVISD::FPCLASS: {
// fclass will only set one of the low 10 bits.
Known.Zero.setBitsFrom(10);
break;
}
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo =
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12 changes: 4 additions & 8 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
Original file line number Diff line number Diff line change
Expand Up @@ -1755,29 +1755,25 @@ define i1 @isqnan_fpclass(float %x) {
; RV32IF-LABEL: isqnan_fpclass:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fclass.s a0, fa0
; RV32IF-NEXT: slli a0, a0, 22
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: srli a0, a0, 9
; RV32IF-NEXT: ret
;
; RV32IZFINX-LABEL: isqnan_fpclass:
; RV32IZFINX: # %bb.0:
; RV32IZFINX-NEXT: fclass.s a0, a0
; RV32IZFINX-NEXT: slli a0, a0, 22
; RV32IZFINX-NEXT: srli a0, a0, 31
; RV32IZFINX-NEXT: srli a0, a0, 9
; RV32IZFINX-NEXT: ret
;
; RV64IF-LABEL: isqnan_fpclass:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fclass.s a0, fa0
; RV64IF-NEXT: slli a0, a0, 54
; RV64IF-NEXT: srli a0, a0, 63
; RV64IF-NEXT: srli a0, a0, 9
; RV64IF-NEXT: ret
;
; RV64IZFINX-LABEL: isqnan_fpclass:
; RV64IZFINX: # %bb.0:
; RV64IZFINX-NEXT: fclass.s a0, a0
; RV64IZFINX-NEXT: slli a0, a0, 54
; RV64IZFINX-NEXT: srli a0, a0, 63
; RV64IZFINX-NEXT: srli a0, a0, 9
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: isqnan_fpclass:
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