[RISCV] Add MC layer support for XSfmm*. (#133031)

This adds assembler/disassembler support for XSfmmbase 0.6 and related
SiFive matrix multiplication extensions based on the spec here
https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification

Functionality-wise, this is the same as the Zvma extension proposal that
SiFive shared with the Attached Matrix Extension Task Group. The
extension names and instruction mnemonics have been changed to use
vendor prefixes.

Note this is a non-conforming extension as the opcodes used here are in
the standard opcode space in OP-V or OP-VE.

---------

Co-authored-by: Brandon Wu <brandon.wu@sifive.com>

Author: topperc

clang/test/Driver/print-supported-extensions-riscv.c

@@ -170,6 +170,16 @@
 // CHECK-NEXT:     xmipscmov            1.0       'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
 // CHECK-NEXT:     xmipslsp             1.0       'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
 // CHECK-NEXT:     xsfcease             1.0       'XSfcease' (SiFive sf.cease Instruction)
+// CHECK-NEXT:     xsfmm128t            0.6       'XSfmm128t' (TE=128 configuration)
+// CHECK-NEXT:     xsfmm16t             0.6       'XSfmm16t' (TE=16 configuration)
+// CHECK-NEXT:     xsfmm32a16f          0.6       'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF))
+// CHECK-NEXT:     xsfmm32a32f          0.6       'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b)
+// CHECK-NEXT:     xsfmm32a8f           0.6       'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)
+// CHECK-NEXT:     xsfmm32a8i           0.6       'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)
+// CHECK-NEXT:     xsfmm32t             0.6       'XSfmm32t' (TE=32 configuration)
+// CHECK-NEXT:     xsfmm64a64f          0.6       'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)
+// CHECK-NEXT:     xsfmm64t             0.6       'XSfmm64t' (TE=64 configuration)
+// CHECK-NEXT:     xsfmmbase            0.6       'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)
 // CHECK-NEXT:     xsfvcp               1.0       'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)
 // CHECK-NEXT:     xsfvfnrclipxfqf      1.0       'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)
 // CHECK-NEXT:     xsfvfwmaccqqq        1.0       'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))

clang/test/Preprocessor/riscv-target-features-sifive.c

@@ -0,0 +1,79 @@
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm128t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM128T %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm128t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM128T %s
+// CHECK-XSFMM128T: __riscv_xsfmm128t  6000{{$}}
+//
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm16t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM16T %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm16t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM16T %s
+// CHECK-XSFMM16T: __riscv_xsfmm16t  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm32a8i -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32a8I %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm32a8i -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32a8I %s
+// CHECK-XSFMM32a8I: __riscv_xsfmm32a8i  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm32a8f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32A8F %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm32a8f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32A8F %s
+// CHECK-XSFMM32A8F: __riscv_xsfmm32a8f  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm32a16f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32a16F %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm32a16f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32a16F %s
+// CHECK-XSFMM32a16F: __riscv_xsfmm32a16f  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm32a32f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32a32F %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm32a32f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32a32F %s
+// CHECK-XSFMM32a32F: __riscv_xsfmm32a32f  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm32t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32T %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm32t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM32T %s
+// CHECK-XSFMM32T: __riscv_xsfmm32t  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm64a64f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM64a64f %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm64a64f -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM64a64f %s
+// CHECK-XSFMM64a64f: __riscv_xsfmm64a64f  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmm64t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM64T %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmm64t -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMM64T %s
+// CHECK-XSFMM64T: __riscv_xsfmm64t  6000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_zve32x_xsfmmbase -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMMBASE %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_zve32x_xsfmmbase -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSFMMBASE %s
+// CHECK-XSFMMBASE: __riscv_xsfmmbase  6000{{$}}

llvm/docs/RISCVUsage.rst

@@ -392,6 +392,9 @@ The current vendor extensions supported are:
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`__ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
+``Xsfmm*``
+  LLVM implements `version 0.6 of the Xsfmm Family of Attached Matrix Extensions Specification <https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification>`__ by SiFive.  All instructions are prefixed with `sf.` as described in the specification.
+
 ``XSfvcp``
   LLVM implements `version 1.1.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/Zn3m1R5LeNNTwnLS_vcix-spec-software-v1p1.pdf>`__ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
 

llvm/docs/ReleaseNotes.md

@@ -197,7 +197,9 @@ Changes to the RISC-V Backend
 * Adds assembler support for the Andes `XAndesvdot` (Andes Vector Dot Product extension).
 * Adds assembler support for the standard `Q` (Quad-Precision Floating Point) 
   extension.
-  
+* Adds experimental assembler support for the SiFive Xsfmm* Attached Matrix
+  Extensions.
+
 Changes to the WebAssembly Backend
 ----------------------------------
 

llvm/include/llvm/TargetParser/RISCVTargetParser.h

@@ -89,6 +89,8 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
 unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
                      bool MaskAgnostic);
 
+unsigned encodeXSfmmVType(unsigned SEW, unsigned Widen, bool AltFmt);
+
 inline static VLMUL getVLMUL(unsigned VType) {
   unsigned VLMul = VType & 0x7;
   return static_cast<VLMUL>(VLMul);
@@ -118,10 +120,34 @@ inline static unsigned getSEW(unsigned VType) {
   return decodeVSEW(VSEW);
 }
 
+inline static unsigned decodeTWiden(unsigned TWiden) {
+  assert((TWiden == 1 || TWiden == 2 || TWiden == 3) &&
+         "Unexpected TWiden value");
+  return 1 << (TWiden - 1);
+}
+
+inline static bool hasXSfmmWiden(unsigned VType) {
+  unsigned TWiden = (VType >> 9) & 0x3;
+  return TWiden != 0;
+}
+
+inline static unsigned getXSfmmWiden(unsigned VType) {
+  unsigned TWiden = (VType >> 9) & 0x3;
+  assert(TWiden != 0 && "Invalid widen value");
+  return 1 << (TWiden - 1);
+}
+
+static inline bool isValidXSfmmVType(unsigned VTypeI) {
+  return (VTypeI & ~0x738) == 0 && RISCVVType::hasXSfmmWiden(VTypeI) &&
+         RISCVVType::getSEW(VTypeI) * RISCVVType::getXSfmmWiden(VTypeI) <= 64;
+}
+
 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
 
 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
 
+inline static bool isAltFmt(unsigned VType) { return VType & 0x100; }
+
 void printVType(unsigned VType, raw_ostream &OS);
 
 unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul);

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -125,6 +125,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
                        bool &MaskAgnostic);
   bool generateVTypeError(SMLoc ErrorLoc);
 
+  bool generateXSfmmVTypeError(SMLoc ErrorLoc);
   // Helper to actually emit an instruction to the MCStreamer. Also, when
   // possible, compression of the instruction is performed.
   void emitToStreamer(MCStreamer &S, const MCInst &Inst);
@@ -221,6 +222,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   }
 
   ParseStatus parseRegReg(OperandVector &Operands);
+  ParseStatus parseXSfmmVType(OperandVector &Operands);
   ParseStatus parseRetval(OperandVector &Operands);
   ParseStatus parseZcmpStackAdj(OperandVector &Operands,
                                 bool ExpectNegative = false);
@@ -634,6 +636,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
     return isUImm<11>();
   }
 
+  bool isXSfmmVType() const {
+    return Kind == KindTy::VType && RISCVVType::isValidXSfmmVType(VType.Val);
+  }
+
   /// Return true if the operand is a valid for the fence instruction e.g.
   /// ('iorw').
   bool isFenceArg() const { return Kind == KindTy::Fence; }
@@ -2342,6 +2348,65 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
       "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
 }
 
+ParseStatus RISCVAsmParser::parseXSfmmVType(OperandVector &Operands) {
+  SMLoc S = getLoc();
+
+  unsigned Widen = 0;
+  unsigned SEW = 0;
+  bool AltFmt = false;
+  StringRef Identifier;
+
+  if (getTok().isNot(AsmToken::Identifier))
+    goto Fail;
+
+  Identifier = getTok().getIdentifier();
+
+  if (!Identifier.consume_front("e"))
+    goto Fail;
+
+  if (Identifier.getAsInteger(10, SEW)) {
+    if (Identifier != "16alt")
+      goto Fail;
+
+    AltFmt = true;
+    SEW = 16;
+  }
+  if (!RISCVVType::isValidSEW(SEW))
+    goto Fail;
+
+  Lex();
+
+  if (!parseOptionalToken(AsmToken::Comma))
+    goto Fail;
+
+  if (getTok().isNot(AsmToken::Identifier))
+    goto Fail;
+
+  Identifier = getTok().getIdentifier();
+
+  if (!Identifier.consume_front("w"))
+    goto Fail;
+  if (Identifier.getAsInteger(10, Widen))
+    goto Fail;
+  if (Widen != 1 && Widen != 2 && Widen != 4)
+    goto Fail;
+
+  Lex();
+
+  if (getLexer().is(AsmToken::EndOfStatement)) {
+    Operands.push_back(RISCVOperand::createVType(
+        RISCVVType::encodeXSfmmVType(SEW, Widen, AltFmt), S));
+    return ParseStatus::Success;
+  }
+
+Fail:
+  return generateXSfmmVTypeError(S);
+}
+
+bool RISCVAsmParser::generateXSfmmVTypeError(SMLoc ErrorLoc) {
+  return Error(ErrorLoc, "operand must be e[8|16|16alt|32|64],w[1|2|4]");
+}
+
 ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
   if (getLexer().isNot(AsmToken::Identifier))
     return ParseStatus::NoMatch;

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -344,6 +344,39 @@ static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
+                                          uint64_t Address,
+                                          const MCDisassembler *Decoder) {
+  if (RegNo > 15)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::T0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  if (RegNo > 15 || RegNo % 2)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::T0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  if (RegNo > 15 || RegNo % 4)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::T0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
                                    uint64_t Address,
                                    const MCDisassembler *Decoder) {
@@ -722,9 +755,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
 };
 
 static constexpr FeatureBitset XSfVectorGroup = {
-    RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
-    RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
-    RISCV::FeatureVendorXSfvfnrclipxfqf};
+    RISCV::FeatureVendorXSfvcp,          RISCV::FeatureVendorXSfvqmaccdod,
+    RISCV::FeatureVendorXSfvqmaccqoq,    RISCV::FeatureVendorXSfvfwmaccqqq,
+    RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
 static constexpr FeatureBitset XSfSystemGroup = {
     RISCV::FeatureVendorXSiFivecdiscarddlone,
     RISCV::FeatureVendorXSiFivecflushdlone,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

@@ -227,6 +227,20 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
   RISCVVType::printVType(Imm, O);
 }
 
+void RISCVInstPrinter::printXSfmmVType(const MCInst *MI, unsigned OpNo,
+                                       const MCSubtargetInfo &STI,
+                                       raw_ostream &O) {
+  unsigned Imm = MI->getOperand(OpNo).getImm();
+  assert(RISCVVType::isValidXSfmmVType(Imm));
+  unsigned SEW = RISCVVType::getSEW(Imm);
+  O << "e" << SEW;
+  bool AltFmt = RISCVVType::isAltFmt(Imm);
+  if (AltFmt)
+    O << "alt";
+  unsigned Widen = RISCVVType::getXSfmmWiden(Imm);
+  O << ", w" << Widen;
+}
+
 // Print a Zcmp RList. If we are printing architectural register names rather
 // than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
 // registers. Otherwise, we print "{ra, s0-s11}".

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

@@ -48,6 +48,8 @@ class RISCVInstPrinter : public MCInstPrinter {
                             const MCSubtargetInfo &STI, raw_ostream &O);
   void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
+  void printXSfmmVType(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
   void printVMaskReg(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
   void printRegList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,