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[IndVarSimplify] Add test requiring ashr expansion.
Add test cases showing large ashr expansion during IndVarSimplify after ec54867.
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‎llvm/test/Transforms/IndVarSimplify/ashr-expansion.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -indvars -S %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define float @ashr_expansion_valid(i64 %x, float* %ptr) {
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; CHECK-LABEL: @ashr_expansion_valid(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[X:%.*]], i64 -1)
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; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[SMAX]], i64 1)
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; CHECK-NEXT: [[TMP0:%.*]] = sub i64 0, [[X]]
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; CHECK-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[X]], i64 [[TMP0]])
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[SMAX1]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = mul nsw i64 [[SMIN]], [[TMP1]]
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP2]], i64 1)
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
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; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
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;
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entry:
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%bound = ashr exact i64 %x, 4
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
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%gep = getelementptr float, float* %ptr, i64 %iv
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%lv = load float, float* %gep
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%red.next = fadd float %lv, %red
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%iv.next = add nuw i64 %iv, 1
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%cond = icmp ult i64 %iv.next, %bound
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br i1 %cond, label %loop, label %exit
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exit: ; preds = %bb135
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%lcssa.red.next = phi float [ %red.next, %loop ]
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ret float %lcssa.red.next
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}
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; No explicit ashr, but a chain of operations that can be replaced by ashr.
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define float @ashr_equivalent_expansion(i64 %x, float* %ptr) {
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; CHECK-LABEL: @ashr_equivalent_expansion(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ABS_X:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 false)
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; CHECK-NEXT: [[T0:%.*]] = call i64 @llvm.smax.i64(i64 [[X]], i64 -1)
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; CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.smin.i64(i64 [[T0]], i64 1)
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; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[ABS_X]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[T1]], [[TMP0]]
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 1)
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
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; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
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;
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entry:
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%abs_x = call i64 @llvm.abs.i64(i64 %x, i1 false)
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%div = udiv exact i64 %abs_x, 16
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%t0 = call i64 @llvm.smax.i64(i64 %x, i64 -1)
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%t1 = call i64 @llvm.smin.i64(i64 %t0, i64 1)
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%bound = mul nsw i64 %div, %t1
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
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%gep = getelementptr float, float* %ptr, i64 %iv
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%lv = load float, float* %gep
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%red.next = fadd float %lv, %red
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%iv.next = add nuw i64 %iv, 1
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%cond = icmp ult i64 %iv.next, %bound
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br i1 %cond, label %loop, label %exit
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exit: ; preds = %bb135
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%lcssa.red.next = phi float [ %red.next, %loop ]
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ret float %lcssa.red.next
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}
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; Chain of operations that *cannot* be replaced by ashr, because the udiv is
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; missing exact.
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define float @no_ashr_due_to_missing_exact_udiv(i64 %x, float* %ptr) {
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; CHECK-LABEL: @no_ashr_due_to_missing_exact_udiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ABS_X:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 false)
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; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[ABS_X]], 16
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; CHECK-NEXT: [[T0:%.*]] = call i64 @llvm.smax.i64(i64 [[X]], i64 -1)
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; CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.smin.i64(i64 [[T0]], i64 1)
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; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[T1]], [[DIV]]
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
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; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
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;
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entry:
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%abs_x = call i64 @llvm.abs.i64(i64 %x, i1 false)
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%div = udiv i64 %abs_x, 16
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%t0 = call i64 @llvm.smax.i64(i64 %x, i64 -1)
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%t1 = call i64 @llvm.smin.i64(i64 %t0, i64 1)
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%bound = mul nsw i64 %div, %t1
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
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%gep = getelementptr float, float* %ptr, i64 %iv
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%lv = load float, float* %gep
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%red.next = fadd float %lv, %red
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%iv.next = add nuw i64 %iv, 1
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%cond = icmp ult i64 %iv.next, %bound
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br i1 %cond, label %loop, label %exit
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exit: ; preds = %bb135
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%lcssa.red.next = phi float [ %red.next, %loop ]
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ret float %lcssa.red.next
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}
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; Chain of operations that *cannot* be replaced by ashr, because abs and
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; signum have different operands.
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define float @no_ashr_due_to_different_ops(i64 %x, i64 %y, float* %ptr) {
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; CHECK-LABEL: @no_ashr_due_to_different_ops(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ABS_X:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 false)
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; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[ABS_X]], 16
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; CHECK-NEXT: [[T0:%.*]] = call i64 @llvm.smax.i64(i64 [[Y:%.*]], i64 -1)
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; CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.smin.i64(i64 [[T0]], i64 1)
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; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[T1]], [[DIV]]
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
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; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
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;
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entry:
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%abs_x = call i64 @llvm.abs.i64(i64 %x, i1 false)
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%div = udiv i64 %abs_x, 16
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%t0 = call i64 @llvm.smax.i64(i64 %y, i64 -1)
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%t1 = call i64 @llvm.smin.i64(i64 %t0, i64 1)
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%bound = mul nsw i64 %div, %t1
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
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%gep = getelementptr float, float* %ptr, i64 %iv
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%lv = load float, float* %gep
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%red.next = fadd float %lv, %red
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%iv.next = add nuw i64 %iv, 1
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%cond = icmp ult i64 %iv.next, %bound
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br i1 %cond, label %loop, label %exit
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exit: ; preds = %bb135
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%lcssa.red.next = phi float [ %red.next, %loop ]
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ret float %lcssa.red.next
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}
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declare i64 @llvm.abs.i64(i64, i1)
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declare i64 @llvm.smax.i64(i64, i64)
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declare i64 @llvm.smin.i64(i64, i64)

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