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13 | 13 |
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14 | 14 | class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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15 | 15 | string asmstr, list<dag> pattern>
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16 |
| - : I<opcode, OOL, IOL, asmstr, NoItinerary> { |
| 16 | + : I<opcode, OOL, IOL, asmstr, NoItinerary> { |
17 | 17 | bits<5> RT;
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18 | 18 | bits<5> RA;
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19 | 19 | bits<5> RB;
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20 | 20 | bit L;
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21 | 21 |
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22 | 22 | let Pattern = pattern;
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23 | 23 |
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24 |
| - bit RC = 0; // set by isRecordForm |
| 24 | + bit RC = 0; // set by isRecordForm |
25 | 25 |
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26 |
| - let Inst{6...10} = RT; |
| 26 | + let Inst{6...10} = RT; |
27 | 27 | let Inst{11...15} = RA;
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28 | 28 | let Inst{16...20} = RB;
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29 |
| - let Inst{21} = L; |
| 29 | + let Inst{21} = L; |
30 | 30 | let Inst{22...30} = xo;
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31 |
| - let Inst{31} = RC; |
| 31 | + let Inst{31} = RC; |
32 | 32 | }
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33 | 33 |
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34 | 34 | multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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35 |
| - string asmbase, string asmstr, |
36 |
| - list<dag> pattern> { |
| 35 | + string asmbase, string asmstr, list<dag> pattern> { |
37 | 36 | let BaseName = asmbase in {
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38 | 37 | def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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39 | 38 | !strconcat(asmbase, !strconcat(" ", asmstr)),
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40 |
| - pattern>, RecFormRel; |
41 |
| - let Defs = [CR0] in |
42 |
| - def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL, |
43 |
| - !strconcat(asmbase, !strconcat(". ", asmstr)), |
44 |
| - []>, isRecordForm, RecFormRel; |
| 39 | + pattern>, |
| 40 | + RecFormRel; |
| 41 | + let Defs = [CR0] in def _rec |
| 42 | + : XOForm_RTAB5_L1<opcode, xo, OOL, IOL, |
| 43 | + !strconcat(asmbase, !strconcat(". ", asmstr)), []>, |
| 44 | + isRecordForm, RecFormRel; |
45 | 45 | }
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46 | 46 | }
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47 | 47 |
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@@ -122,39 +122,40 @@ class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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122 | 122 |
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123 | 123 | let Predicates = [IsISAFuture] in {
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124 | 124 | defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
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125 |
| - (ins g8rc:$RA, g8rc:$RB, u1imm:$L), |
126 |
| - "subfus", "$RT, $L, $RA, $RB", []>; |
| 125 | + (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus", |
| 126 | + "$RT, $L, $RA, $RB", []>; |
127 | 127 | }
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128 | 128 |
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129 | 129 | let Predicates = [HasVSX, IsISAFuture] in {
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130 | 130 | let mayLoad = 1 in {
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131 |
| - def LXVRL |
132 |
| - : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), |
133 |
| - "lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>; |
134 |
| - def LXVRLL |
135 |
| - : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), |
136 |
| - "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>; |
137 |
| - def LXVPRL |
138 |
| - : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), (ins (memr $RA):$addr, g8rc:$RB), |
139 |
| - "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>; |
140 |
| - def LXVPRLL |
141 |
| - : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), (ins (memr $RA):$addr, g8rc:$RB), |
142 |
| - "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; |
| 131 | + def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), |
| 132 | + (ins (memr $RA):$addr, g8rc:$RB), |
| 133 | + "lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>; |
| 134 | + def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), |
| 135 | + (ins (memr $RA):$addr, g8rc:$RB), |
| 136 | + "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>; |
| 137 | + def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), |
| 138 | + (ins (memr $RA):$addr, g8rc:$RB), |
| 139 | + "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>; |
| 140 | + def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), |
| 141 | + (ins (memr $RA):$addr, g8rc:$RB), |
| 142 | + "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; |
143 | 143 | }
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144 | 144 |
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145 | 145 | let mayStore = 1 in {
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146 |
| - def STXVRL |
147 |
| - : XX1Form_memOp<31, 653, (outs), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), |
148 |
| - "stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>; |
149 |
| - def STXVRLL |
150 |
| - : XX1Form_memOp<31, 685, (outs), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), |
151 |
| - "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>; |
| 146 | + def STXVRL : XX1Form_memOp<31, 653, (outs), |
| 147 | + (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), |
| 148 | + "stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>; |
| 149 | + def STXVRLL : XX1Form_memOp<31, 685, (outs), |
| 150 | + (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), |
| 151 | + "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>; |
152 | 152 | def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
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153 | 153 | (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
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154 | 154 | "stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
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155 |
| - def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs), |
156 |
| - (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB), |
157 |
| - "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; |
| 155 | + def STXVPRLL |
| 156 | + : XForm_XTp5_XAB5<31, 749, (outs), |
| 157 | + (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB), |
| 158 | + "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; |
158 | 159 | }
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159 | 160 |
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160 | 161 | def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),
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