Skip to content

Commit cc5d636

Browse files
committed
[RISCV] Add PseudoCCANDN/ORN/XNOR to isSignExtendedW.
This matches PseudoCCAND/OR/XOR
1 parent 1ecdbf2 commit cc5d636

File tree

1 file changed

+6
-0
lines changed

1 file changed

+6
-0
lines changed

llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -568,6 +568,9 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
568568
case RISCV::PseudoCCAND:
569569
case RISCV::PseudoCCOR:
570570
case RISCV::PseudoCCXOR:
571+
case RISCV::PseudoCCANDN:
572+
case RISCV::PseudoCCORN:
573+
case RISCV::PseudoCCXNOR:
571574
case RISCV::PHI: {
572575
// If all incoming values are sign-extended, the output of AND, OR, XOR,
573576
// MIN, MAX, or PHI is also sign-extended.
@@ -590,6 +593,9 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
590593
case RISCV::PseudoCCAND:
591594
case RISCV::PseudoCCOR:
592595
case RISCV::PseudoCCXOR:
596+
case RISCV::PseudoCCANDN:
597+
case RISCV::PseudoCCORN:
598+
case RISCV::PseudoCCXNOR:
593599
B = 4;
594600
E = 7;
595601
break;

0 commit comments

Comments
 (0)