[amdgpu] Skip OR combining on 64-bit integer before legalizing ops.

darkbuck · darkbuck · commit ec02635d104c · 2020-06-12T15:22:38.000-04:00
Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81710
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8958,7 +8958,7 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
     }
   }
 
-  if (VT != MVT::i64)
+  if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
     return SDValue();
 
   // TODO: This could be a generic combine with a predicate for extracting the
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -763,7 +763,7 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
 ; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
 ; SI-NEXT:    v_and_b32_e32 v2, v9, v1
-; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; SI-NEXT:    v_alignbit_b32 v1, v1, v0, 16
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: v_fshr_v3i16:

Original file line number	Diff line number	Diff line change
`@@ -8958,7 +8958,7 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,`
`8958`	`8958`	`}`
`8959`	`8959`	`}`
`8960`	`8960`
`8961`		`- if (VT != MVT::i64)`
	`8961`	`+ if (VT != MVT::i64 \|\| DCI.isBeforeLegalizeOps())`
`8962`	`8962`	`return SDValue();`
`8963`	`8963`
`8964`	`8964`	`// TODO: This could be a generic combine with a predicate for extracting the`
Original file line number	Diff line number	Diff line change
`@@ -763,7 +763,7 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2`
`763`	`763`	`; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1`
`764`	`764`	`; SI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc`
`765`	`765`	`; SI-NEXT: v_and_b32_e32 v2, v9, v1`
`766`		`-; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16`
	`766`	`+; SI-NEXT: v_alignbit_b32 v1, v1, v0, 16`
`767`	`767`	`; SI-NEXT: s_setpc_b64 s[30:31]`
`768`	`768`	`;`
`769`	`769`	`; VI-LABEL: v_fshr_v3i16:`