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[ARM] Testing for stored extracted values. NFC
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‎llvm/test/CodeGen/Thumb2/mve-extractstore.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
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define half @extret1_f16_sf(<8 x half> %a, <8 x half> %b, half* nocapture %p) {
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; CHECK-LABEL: extret1_f16_sf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r6, r7, lr}
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; CHECK-NEXT: push {r4, r6, r7, lr}
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; CHECK-NEXT: .setfp r7, sp, #8
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; CHECK-NEXT: add r7, sp, #8
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: mov r4, sp
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; CHECK-NEXT: bfc r4, #0, #4
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; CHECK-NEXT: mov sp, r4
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; CHECK-NEXT: strd r0, r1, [sp]
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; CHECK-NEXT: add.w r0, r7, #8
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; CHECK-NEXT: mov r1, sp
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: sub.w r4, r7, #8
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; CHECK-NEXT: ldr r0, [r7, #24]
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; CHECK-NEXT: vadd.f16 q0, q1, q0
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; CHECK-NEXT: vmovx.f16 s0, s0
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; CHECK-NEXT: vstr.16 s0, [r0]
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: mov sp, r4
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; CHECK-NEXT: pop {r4, r6, r7, pc}
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%c = fadd <8 x half> %a, %b
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%e = extractelement <8 x half> %c, i32 1
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store half %e, half* %p, align 2
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ret half %e
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}
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define half @extret4_f16_sf(<8 x half> %a, <8 x half> %b, half* nocapture %p) {
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; CHECK-LABEL: extret4_f16_sf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vmov d1, r2, r3
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: ldr r0, [sp, #16]
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; CHECK-NEXT: vadd.f16 q0, q0, q1
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; CHECK-NEXT: vstr.16 s2, [r0]
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: bx lr
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%c = fadd <8 x half> %a, %b
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%e = extractelement <8 x half> %c, i32 4
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store half %e, half* %p, align 2
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ret half %e
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}
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define arm_aapcs_vfpcc half @extret1_f16_hf(<8 x half> %a, <8 x half> %b, half* nocapture %p) {
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; CHECK-LABEL: extret1_f16_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f16 q0, q0, q1
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; CHECK-NEXT: vmovx.f16 s0, s0
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; CHECK-NEXT: vstr.16 s0, [r0]
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; CHECK-NEXT: bx lr
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%c = fadd <8 x half> %a, %b
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%e = extractelement <8 x half> %c, i32 1
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store half %e, half* %p, align 2
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ret half %e
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}
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define arm_aapcs_vfpcc half @extret4_f16_hf(<8 x half> %a, <8 x half> %b, half* nocapture %p) {
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; CHECK-LABEL: extret4_f16_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f16 q0, q0, q1
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; CHECK-NEXT: vmov.f32 s0, s2
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; CHECK-NEXT: vstr.16 s2, [r0]
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; CHECK-NEXT: bx lr
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%c = fadd <8 x half> %a, %b
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%e = extractelement <8 x half> %c, i32 4
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store half %e, half* %p, align 2
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ret half %e
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}
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define arm_aapcs_vfpcc <8 x half> @extret1_v8f16_hf(<8 x half> %a, <8 x half> %b, half* nocapture %p) {
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; CHECK-LABEL: extret1_v8f16_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f16 q0, q0, q1
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; CHECK-NEXT: vmovx.f16 s4, s0
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; CHECK-NEXT: vstr.16 s4, [r0]
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; CHECK-NEXT: vmov.u16 r0, q0[1]
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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%c = fadd <8 x half> %a, %b
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%e = extractelement <8 x half> %c, i32 1
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store half %e, half* %p, align 2
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%i = insertelement <8 x half> undef, half %e, i32 0
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%s = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
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ret <8 x half> %s
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}
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define arm_aapcs_vfpcc <8 x half> @extret4_v8f16_hf(<8 x half> %a, <8 x half> %b, half* nocapture %p) {
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; CHECK-LABEL: extret4_v8f16_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f16 q0, q0, q1
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; CHECK-NEXT: vstr.16 s2, [r0]
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; CHECK-NEXT: vmov.u16 r0, q0[4]
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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%c = fadd <8 x half> %a, %b
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%e = extractelement <8 x half> %c, i32 4
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store half %e, half* %p, align 2
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%i = insertelement <8 x half> undef, half %e, i32 0
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%s = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
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ret <8 x half> %s
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}
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define float @extret1_f32_sf(<4 x float> %a, <4 x float> %b, float* nocapture %p) {
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; CHECK-LABEL: extret1_f32_sf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r6, r7, lr}
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; CHECK-NEXT: push {r4, r6, r7, lr}
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; CHECK-NEXT: .setfp r7, sp, #8
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; CHECK-NEXT: add r7, sp, #8
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: mov r4, sp
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; CHECK-NEXT: bfc r4, #0, #4
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; CHECK-NEXT: mov sp, r4
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; CHECK-NEXT: strd r0, r1, [sp]
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; CHECK-NEXT: add.w r0, r7, #8
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; CHECK-NEXT: mov r1, sp
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: ldr r1, [r7, #24]
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; CHECK-NEXT: sub.w r4, r7, #8
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; CHECK-NEXT: vadd.f32 q0, q1, q0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: vstr s1, [r1]
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; CHECK-NEXT: mov sp, r4
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; CHECK-NEXT: pop {r4, r6, r7, pc}
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%c = fadd <4 x float> %a, %b
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%e = extractelement <4 x float> %c, i32 1
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store float %e, float* %p, align 4
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ret float %e
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}
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define float @extret2_f32_sf(<4 x float> %a, <4 x float> %b, float* nocapture %p) {
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; CHECK-LABEL: extret2_f32_sf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vmov d1, r2, r3
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: ldr r1, [sp, #16]
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; CHECK-NEXT: vadd.f32 q0, q0, q1
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vstr s2, [r1]
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; CHECK-NEXT: bx lr
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%c = fadd <4 x float> %a, %b
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%e = extractelement <4 x float> %c, i32 2
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store float %e, float* %p, align 4
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ret float %e
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}
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define arm_aapcs_vfpcc float @extret1_f32_hf(<4 x float> %a, <4 x float> %b, float* nocapture %p) {
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; CHECK-LABEL: extret1_f32_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f32 q0, q0, q1
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; CHECK-NEXT: vmov.f32 s0, s1
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; CHECK-NEXT: vstr s1, [r0]
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; CHECK-NEXT: bx lr
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%c = fadd <4 x float> %a, %b
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%e = extractelement <4 x float> %c, i32 1
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store float %e, float* %p, align 4
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ret float %e
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}
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define arm_aapcs_vfpcc float @extret2_f32_hf(<4 x float> %a, <4 x float> %b, float* nocapture %p) {
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; CHECK-LABEL: extret2_f32_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f32 q0, q0, q1
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; CHECK-NEXT: vmov.f32 s0, s2
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; CHECK-NEXT: vstr s2, [r0]
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; CHECK-NEXT: bx lr
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%c = fadd <4 x float> %a, %b
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%e = extractelement <4 x float> %c, i32 2
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store float %e, float* %p, align 4
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ret float %e
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}
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define arm_aapcs_vfpcc <4 x float> @extret1_v4f32_hf(<4 x float> %a, <4 x float> %b, float* nocapture %p) {
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; CHECK-LABEL: extret1_v4f32_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f32 q1, q0, q1
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; CHECK-NEXT: vmov r1, s5
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; CHECK-NEXT: vstr s5, [r0]
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; CHECK-NEXT: vdup.32 q0, r1
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; CHECK-NEXT: bx lr
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%c = fadd <4 x float> %a, %b
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%e = extractelement <4 x float> %c, i32 1
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store float %e, float* %p, align 4
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%i = insertelement <4 x float> undef, float %e, i32 0
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%s = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %s
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}
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define arm_aapcs_vfpcc <4 x float> @extret2_v4f32_hf(<4 x float> %a, <4 x float> %b, float* nocapture %p) {
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; CHECK-LABEL: extret2_v4f32_hf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f32 q1, q0, q1
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; CHECK-NEXT: vmov r1, s6
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; CHECK-NEXT: vstr s6, [r0]
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; CHECK-NEXT: vdup.32 q0, r1
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; CHECK-NEXT: bx lr
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%c = fadd <4 x float> %a, %b
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%e = extractelement <4 x float> %c, i32 2
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store float %e, float* %p, align 4
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%i = insertelement <4 x float> undef, float %e, i32 0
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%s = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %s
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}

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