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[X86] Correct types in tablegen multiclasses found by D95874.
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D95926
1 parent 08274d7 commit fae6d12

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6 files changed

+73
-72
lines changed

6 files changed

+73
-72
lines changed

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -914,8 +914,8 @@ def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
914914
// bitcasts and check for either opcode, except when used as a pattern root.
915915
// When used as a pattern root, only fixed-length build_vector and scalable
916916
// splat_vector are supported.
917-
def immAllOnesV; // ISD::isConstantSplatVectorAllOnes
918-
def immAllZerosV; // ISD::isConstantSplatVectorAllZeros
917+
def immAllOnesV : SDPatternOperator; // ISD::isConstantSplatVectorAllOnes
918+
def immAllZerosV : SDPatternOperator; // ISD::isConstantSplatVectorAllZeros
919919

920920
// Other helper fragments.
921921
def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 38 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -3297,15 +3297,15 @@ let Predicates = [HasBWI, NoVLX] in {
32973297
}
32983298

32993299
// Mask setting all 0s or 1s
3300-
multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
3300+
multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, SDPatternOperator Val> {
33013301
let Predicates = [HasAVX512] in
33023302
let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1,
33033303
SchedRW = [WriteZero] in
33043304
def NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
33053305
[(set KRC:$dst, (VT Val))]>;
33063306
}
33073307

3308-
multiclass avx512_mask_setop_w<PatFrag Val> {
3308+
multiclass avx512_mask_setop_w<SDPatternOperator Val> {
33093309
defm W : avx512_mask_setop<VK16, v16i1, Val>;
33103310
defm D : avx512_mask_setop<VK32, v32i1, Val>;
33113311
defm Q : avx512_mask_setop<VK64, v64i1, Val>;
@@ -5300,7 +5300,7 @@ defm : avx512_logical_lowering_types<"VPANDN", X86andnp>;
53005300
//===----------------------------------------------------------------------===//
53015301

53025302
multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5303-
SDNode OpNode, SDNode VecNode,
5303+
SDPatternOperator OpNode, SDNode VecNode,
53045304
X86FoldableSchedWrite sched, bit IsCommutable> {
53055305
let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
53065306
defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
@@ -5390,7 +5390,7 @@ multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
53905390
}
53915391
}
53925392

5393-
multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
5393+
multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
53945394
SDNode VecNode, SDNode RndNode,
53955395
X86SchedWriteSizes sched, bit IsCommutable> {
53965396
defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
@@ -6429,7 +6429,7 @@ let Predicates = [HasAVX512] in {
64296429
// FMA - Fused Multiply Operations
64306430
//
64316431

6432-
multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6432+
multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
64336433
SDNode MaskOpNode, X86FoldableSchedWrite sched,
64346434
X86VectorVTInfo _, string Suff> {
64356435
let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
@@ -6473,7 +6473,7 @@ multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
64736473
AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>;
64746474
}
64756475

6476-
multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6476+
multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
64776477
SDNode MaskOpNode, SDNode OpNodeRnd,
64786478
X86SchedWriteWidths sched,
64796479
AVX512VLVectorVTInfo _, string Suff> {
@@ -6494,7 +6494,7 @@ multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
64946494
}
64956495
}
64966496

6497-
multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
6497+
multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
64986498
SDNode MaskOpNode, SDNode OpNodeRnd> {
64996499
defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode,
65006500
OpNodeRnd, SchedWriteFMA,
@@ -6518,7 +6518,7 @@ defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86any_Fnmsub,
65186518
X86Fnmsub, X86FnmsubRnd>;
65196519

65206520

6521-
multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6521+
multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
65226522
SDNode MaskOpNode, X86FoldableSchedWrite sched,
65236523
X86VectorVTInfo _, string Suff> {
65246524
let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
@@ -6564,7 +6564,7 @@ multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
65646564
1, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>;
65656565
}
65666566

6567-
multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6567+
multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
65686568
SDNode MaskOpNode, SDNode OpNodeRnd,
65696569
X86SchedWriteWidths sched,
65706570
AVX512VLVectorVTInfo _, string Suff> {
@@ -6585,7 +6585,7 @@ multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
65856585
}
65866586
}
65876587

6588-
multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
6588+
multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
65896589
SDNode MaskOpNode, SDNode OpNodeRnd > {
65906590
defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode,
65916591
OpNodeRnd, SchedWriteFMA,
@@ -6608,7 +6608,7 @@ defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86any_Fnmadd,
66086608
defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86any_Fnmsub,
66096609
X86Fnmsub, X86FnmsubRnd>;
66106610

6611-
multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6611+
multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
66126612
SDNode MaskOpNode, X86FoldableSchedWrite sched,
66136613
X86VectorVTInfo _, string Suff> {
66146614
let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
@@ -6656,7 +6656,7 @@ multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
66566656
1, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>;
66576657
}
66586658

6659-
multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6659+
multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
66606660
SDNode MaskOpNode, SDNode OpNodeRnd,
66616661
X86SchedWriteWidths sched,
66626662
AVX512VLVectorVTInfo _, string Suff> {
@@ -6677,7 +6677,7 @@ multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
66776677
}
66786678
}
66796679

6680-
multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
6680+
multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
66816681
SDNode MaskOpNode, SDNode OpNodeRnd > {
66826682
defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode,
66836683
OpNodeRnd, SchedWriteFMA,
@@ -6745,7 +6745,7 @@ let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
67456745
}
67466746

67476747
multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
6748-
string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd,
6748+
string OpcodeStr, SDPatternOperator OpNode, SDNode OpNodeRnd,
67496749
X86VectorVTInfo _, string SUFF> {
67506750
let ExeDomain = _.ExeDomain in {
67516751
defm NAME#213#SUFF#Z: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix, _,
@@ -6779,7 +6779,7 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
67796779
}
67806780

67816781
multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
6782-
string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> {
6782+
string OpcodeStr, SDPatternOperator OpNode, SDNode OpNodeRnd> {
67836783
let Predicates = [HasAVX512] in {
67846784
defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
67856785
OpNodeRnd, f32x_info, "SS">,
@@ -6795,7 +6795,7 @@ defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86any_Fmsub, X86FmsubRn
67956795
defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86any_Fnmadd, X86FnmaddRnd>;
67966796
defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86any_Fnmsub, X86FnmsubRnd>;
67976797

6798-
multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode MaskedOp,
6798+
multiclass avx512_scalar_fma_patterns<SDPatternOperator Op, SDNode MaskedOp,
67996799
SDNode RndOp, string Prefix,
68006800
string Suffix, SDNode Move,
68016801
X86VectorVTInfo _, PatLeaf ZeroFP> {
@@ -7408,7 +7408,7 @@ def : Pat<(v2f64 (X86Movsd
74087408

74097409
// Convert float/double to signed/unsigned int 32/64 with truncation
74107410
multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
7411-
X86VectorVTInfo _DstRC, SDNode OpNode,
7411+
X86VectorVTInfo _DstRC, SDPatternOperator OpNode,
74127412
SDNode OpNodeInt, SDNode OpNodeSAE,
74137413
X86FoldableSchedWrite sched, string aliasStr>{
74147414
let Predicates = [HasAVX512], ExeDomain = _SrcRC.ExeDomain in {
@@ -7595,7 +7595,7 @@ def : Pat<(v2f64 (X86Movsd
75957595
//===----------------------------------------------------------------------===//
75967596

75977597
multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7598-
X86VectorVTInfo _Src, SDNode OpNode, SDNode MaskOpNode,
7598+
X86VectorVTInfo _Src, SDPatternOperator OpNode, SDPatternOperator MaskOpNode,
75997599
X86FoldableSchedWrite sched,
76007600
string Broadcast = _.BroadcastStr,
76017601
string Alias = "", X86MemOperand MemOp = _Src.MemOp,
@@ -7665,7 +7665,7 @@ multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
76657665

76667666
// Conversion with rounding control (RC)
76677667
multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7668-
X86VectorVTInfo _Src, SDNode OpNodeRnd,
7668+
X86VectorVTInfo _Src, SDPatternOperator OpNodeRnd,
76697669
X86FoldableSchedWrite sched> {
76707670
let Uses = [MXCSR] in
76717671
defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
@@ -7677,8 +7677,8 @@ multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
76777677

76787678
// Similar to avx512_vcvt_fp, but uses an extload for the memory form.
76797679
multiclass avx512_vcvt_fpextend<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
7680-
X86VectorVTInfo _Src, SDNode OpNode,
7681-
SDNode MaskOpNode,
7680+
X86VectorVTInfo _Src, SDPatternOperator OpNode,
7681+
SDNode MaskOpNode,
76827682
X86FoldableSchedWrite sched,
76837683
string Broadcast = _.BroadcastStr,
76847684
string Alias = "", X86MemOperand MemOp = _Src.MemOp,
@@ -7802,8 +7802,8 @@ let Predicates = [HasVLX] in {
78027802

78037803
// Convert Signed/Unsigned Doubleword to Double
78047804
let Uses = []<Register>, mayRaiseFPException = 0 in
7805-
multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
7806-
SDNode MaskOpNode, SDNode OpNode128,
7805+
multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
7806+
SDNode MaskOpNode, SDPatternOperator OpNode128,
78077807
SDNode MaskOpNode128,
78087808
X86SchedWriteWidths sched> {
78097809
// No rounding in this op
@@ -7828,7 +7828,7 @@ multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
78287828
}
78297829

78307830
// Convert Signed/Unsigned Doubleword to Float
7831-
multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
7831+
multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
78327832
SDNode MaskOpNode, SDNode OpNodeRnd,
78337833
X86SchedWriteWidths sched> {
78347834
let Predicates = [HasAVX512] in
@@ -7846,7 +7846,7 @@ multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
78467846
}
78477847

78487848
// Convert Float to Signed/Unsigned Doubleword with truncation
7849-
multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
7849+
multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
78507850
SDNode MaskOpNode,
78517851
SDNode OpNodeSAE, X86SchedWriteWidths sched> {
78527852
let Predicates = [HasAVX512] in {
@@ -7882,7 +7882,7 @@ multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
78827882
}
78837883

78847884
// Convert Double to Signed/Unsigned Doubleword with truncation
7885-
multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
7885+
multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
78867886
SDNode MaskOpNode, SDNode OpNodeSAE,
78877887
X86SchedWriteWidths sched> {
78887888
let Predicates = [HasAVX512] in {
@@ -8028,7 +8028,7 @@ multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
80288028
}
80298029

80308030
// Convert Double to Signed/Unsigned Quardword with truncation
8031-
multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
8031+
multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
80328032
SDNode MaskOpNode, SDNode OpNodeRnd,
80338033
X86SchedWriteWidths sched> {
80348034
let Predicates = [HasDQI] in {
@@ -8046,7 +8046,7 @@ multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
80468046
}
80478047

80488048
// Convert Signed/Unsigned Quardword to Double
8049-
multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
8049+
multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
80508050
SDNode MaskOpNode, SDNode OpNodeRnd,
80518051
X86SchedWriteWidths sched> {
80528052
let Predicates = [HasDQI] in {
@@ -8091,7 +8091,7 @@ multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
80918091
}
80928092

80938093
// Convert Float to Signed/Unsigned Quardword with truncation
8094-
multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
8094+
multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
80958095
SDNode MaskOpNode, SDNode OpNodeRnd,
80968096
X86SchedWriteWidths sched> {
80978097
let Predicates = [HasDQI] in {
@@ -8118,7 +8118,7 @@ multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
81188118
}
81198119

81208120
// Convert Signed/Unsigned Quardword to Float
8121-
multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
8121+
multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
81228122
SDNode MaskOpNode, SDNode OpNodeRnd,
81238123
X86SchedWriteWidths sched> {
81248124
let Predicates = [HasDQI] in {
@@ -10094,7 +10094,8 @@ defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", WriteVarShuffle256,
1009410094
// op(broadcast(eltVt),imm)
1009510095
//all instruction created with FROUND_CURRENT
1009610096
multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr,
10097-
SDNode OpNode, SDNode MaskOpNode,
10097+
SDPatternOperator OpNode,
10098+
SDPatternOperator MaskOpNode,
1009810099
X86FoldableSchedWrite sched,
1009910100
X86VectorVTInfo _> {
1010010101
let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
@@ -10139,8 +10140,8 @@ multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
1013910140
}
1014010141

1014110142
multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
10142-
AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode,
10143-
SDNode MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched,
10143+
AVX512VLVectorVTInfo _, bits<8> opc, SDPatternOperator OpNode,
10144+
SDPatternOperator MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched,
1014410145
Predicate prd>{
1014510146
let Predicates = [prd] in {
1014610147
defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, MaskOpNode,
@@ -10338,8 +10339,8 @@ multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
1033810339
}
1033910340

1034010341
multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
10341-
bits<8> opcPs, bits<8> opcPd, SDNode OpNode,
10342-
SDNode MaskOpNode, SDNode OpNodeSAE,
10342+
bits<8> opcPs, bits<8> opcPd, SDPatternOperator OpNode,
10343+
SDPatternOperator MaskOpNode, SDNode OpNodeSAE,
1034310344
X86SchedWriteWidths sched, Predicate prd>{
1034410345
defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
1034510346
opcPs, OpNode, MaskOpNode, OpNodeSAE, sched, prd>,
@@ -11563,7 +11564,7 @@ defm VFIXUPIMMPD : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f64_info,
1156311564

1156411565
// TODO: Some canonicalization in lowering would simplify the number of
1156511566
// patterns we have to try to match.
11566-
multiclass AVX512_scalar_math_fp_patterns<SDNode Op, SDNode MaskedOp,
11567+
multiclass AVX512_scalar_math_fp_patterns<SDPatternOperator Op, SDNode MaskedOp,
1156711568
string OpcPrefix, SDNode MoveNode,
1156811569
X86VectorVTInfo _, PatLeaf ZeroFP> {
1156911570
let Predicates = [HasAVX512] in {
@@ -11635,7 +11636,7 @@ defm : AVX512_scalar_math_fp_patterns<any_fsub, fsub, "SUBSD", X86Movsd, v2f64x_
1163511636
defm : AVX512_scalar_math_fp_patterns<any_fmul, fmul, "MULSD", X86Movsd, v2f64x_info, fp64imm0>;
1163611637
defm : AVX512_scalar_math_fp_patterns<any_fdiv, fdiv, "DIVSD", X86Movsd, v2f64x_info, fp64imm0>;
1163711638

11638-
multiclass AVX512_scalar_unary_math_patterns<SDNode OpNode, string OpcPrefix,
11639+
multiclass AVX512_scalar_unary_math_patterns<SDPatternOperator OpNode, string OpcPrefix,
1163911640
SDNode Move, X86VectorVTInfo _> {
1164011641
let Predicates = [HasAVX512] in {
1164111642
def : Pat<(_.VT (Move _.VT:$dst,

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