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Fixed warnings in target/parser codes produced by -Wbitwise-instead-of-logicala
1 parent 5f2f611 commit fb84aa2

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5 files changed

+12
-11
lines changed

5 files changed

+12
-11
lines changed

clang/lib/Lex/PPExpressions.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -662,7 +662,7 @@ static bool EvaluateDirectiveSubExpr(PPValue &LHS, unsigned MinPrec,
662662
case tok::ampamp: // Logical && does not do UACs.
663663
break; // No UAC
664664
default:
665-
Res.setIsUnsigned(LHS.isUnsigned()|RHS.isUnsigned());
665+
Res.setIsUnsigned(LHS.isUnsigned() || RHS.isUnsigned());
666666
// If this just promoted something from signed to unsigned, and if the
667667
// value was negative, warn about it.
668668
if (ValueLive && Res.isUnsigned()) {
@@ -822,7 +822,7 @@ static bool EvaluateDirectiveSubExpr(PPValue &LHS, unsigned MinPrec,
822822

823823
// Usual arithmetic conversions (C99 6.3.1.8p1): result is unsigned if
824824
// either operand is unsigned.
825-
Res.setIsUnsigned(RHS.isUnsigned() | AfterColonVal.isUnsigned());
825+
Res.setIsUnsigned(RHS.isUnsigned() || AfterColonVal.isUnsigned());
826826

827827
// Figure out the precedence of the token after the : part.
828828
PeekPrec = getPrecedence(PeekTok.getKind());

llvm/lib/AsmParser/LLParser.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8529,8 +8529,8 @@ bool LLParser::parseOptionalFFlags(FunctionSummary::FFlags &FFlags) {
85298529
assert(Lex.getKind() == lltok::kw_funcFlags);
85308530
Lex.Lex();
85318531

8532-
if ((int)parseToken(lltok::colon, "expected ':' in funcFlags") |
8533-
(int)parseToken(lltok::lparen, "expected '(' in funcFlags"))
8532+
if (parseToken(lltok::colon, "expected ':' in funcFlags") ||
8533+
parseToken(lltok::lparen, "expected '(' in funcFlags"))
85348534
return true;
85358535

85368536
do {
@@ -8609,7 +8609,7 @@ bool LLParser::parseOptionalCalls(std::vector<FunctionSummary::EdgeTy> &Calls) {
86098609
assert(Lex.getKind() == lltok::kw_calls);
86108610
Lex.Lex();
86118611

8612-
if (parseToken(lltok::colon, "expected ':' in calls") |
8612+
if (parseToken(lltok::colon, "expected ':' in calls") ||
86138613
parseToken(lltok::lparen, "expected '(' in calls"))
86148614
return true;
86158615

@@ -8701,8 +8701,8 @@ bool LLParser::parseOptionalVTableFuncs(VTableFuncList &VTableFuncs) {
87018701
assert(Lex.getKind() == lltok::kw_vTableFuncs);
87028702
Lex.Lex();
87038703

8704-
if ((int)parseToken(lltok::colon, "expected ':' in vTableFuncs") |
8705-
(int)parseToken(lltok::lparen, "expected '(' in vTableFuncs"))
8704+
if (parseToken(lltok::colon, "expected ':' in vTableFuncs") ||
8705+
parseToken(lltok::lparen, "expected '(' in vTableFuncs"))
87068706
return true;
87078707

87088708
IdToIndexMapType IdToIndexMap;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1826,8 +1826,9 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
18261826
.add(I.getOperand(2))
18271827
.add(I.getOperand(3));
18281828

1829-
bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) |
1830-
constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
1829+
bool Ret = false;
1830+
Ret |= constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
1831+
Ret |= constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
18311832
I.eraseFromParent();
18321833
return Ret;
18331834
}

llvm/lib/Target/Lanai/LanaiAluCode.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ inline static unsigned makePostOp(unsigned AluOp) {
7070
}
7171

7272
inline static bool modifiesOp(unsigned AluOp) {
73-
return isPreOp(AluOp) | isPostOp(AluOp);
73+
return isPreOp(AluOp) || isPostOp(AluOp);
7474
}
7575

7676
inline static const char *lanaiAluCodeToString(unsigned AluOp) {

llvm/lib/Target/Mips/MipsSubtarget.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
7878
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
7979
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
8080
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
81-
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
81+
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 || Mips_Os16),
8282
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
8383
HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
8484
HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),

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