[X86] Add USER_MSR instructions. #68944
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For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-clang Author: Freddy Ye (FreddyLeaf) ChangesFor more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Patch is 29.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/68944.diff 35 Files Affected:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 31969201a1cac8c..5300f8458760809 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -538,6 +538,9 @@ X86 Support
- Added option ``-m[no-]evex512`` to disable ZMM and 64-bit mask instructions
for AVX512 features.
+- Support ISA of ``USER_MSR``.
+ * Support intrinsic of ``_urdmsr``.
+ * Support intrinsic of ``_uwrmsr``.
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/clang/include/clang/Basic/BuiltinsX86_64.def b/clang/include/clang/Basic/BuiltinsX86_64.def
index e5c1fe8b319217e..5e00916d4b25ae3 100644
--- a/clang/include/clang/Basic/BuiltinsX86_64.def
+++ b/clang/include/clang/Basic/BuiltinsX86_64.def
@@ -104,6 +104,9 @@ TARGET_BUILTIN(__builtin_ia32_clui, "v", "n", "uintr")
TARGET_BUILTIN(__builtin_ia32_stui, "v", "n", "uintr")
TARGET_BUILTIN(__builtin_ia32_testui, "Uc", "n", "uintr")
TARGET_BUILTIN(__builtin_ia32_senduipi, "vUWi", "n", "uintr")
+// USERMSR
+TARGET_BUILTIN(__builtin_ia32_urdmsr, "ULLiULLi", "n", "usermsr")
+TARGET_BUILTIN(__builtin_ia32_uwrmsr, "vULLiULLi", "n", "usermsr")
// AMX internal builtin
TARGET_BUILTIN(__builtin_ia32_tile_loadconfig_internal, "vvC*", "n", "amx-tile")
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 3f2058a5d4650ca..f0ee6eba67374d8 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5904,6 +5904,8 @@ def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;
def mno_tsxldtrk : Flag<["-"], "mno-tsxldtrk">, Group<m_x86_Features_Group>;
def muintr : Flag<["-"], "muintr">, Group<m_x86_Features_Group>;
def mno_uintr : Flag<["-"], "mno-uintr">, Group<m_x86_Features_Group>;
+def musermsr : Flag<["-"], "musermsr">, Group<m_x86_Features_Group>;
+def mno_usermsr : Flag<["-"], "mno-usermsr">, Group<m_x86_Features_Group>;
def mvaes : Flag<["-"], "mvaes">, Group<m_x86_Features_Group>;
def mno_vaes : Flag<["-"], "mno-vaes">, Group<m_x86_Features_Group>;
def mvpclmulqdq : Flag<["-"], "mvpclmulqdq">, Group<m_x86_Features_Group>;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 022d5753135e160..bea5c52a7b8d7c9 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -376,6 +376,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasTSXLDTRK = true;
} else if (Feature == "+uintr") {
HasUINTR = true;
+ } else if (Feature == "+usermsr") {
+ HasUSERMSR = true;
} else if (Feature == "+crc32") {
HasCRC32 = true;
} else if (Feature == "+x87") {
@@ -869,6 +871,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__TSXLDTRK__");
if (HasUINTR)
Builder.defineMacro("__UINTR__");
+ if (HasUSERMSR)
+ Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
@@ -1053,6 +1057,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("tbm", true)
.Case("tsxldtrk", true)
.Case("uintr", true)
+ .Case("usermsr", true)
.Case("vaes", true)
.Case("vpclmulqdq", true)
.Case("wbnoinvd", true)
@@ -1162,6 +1167,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("tbm", HasTBM)
.Case("tsxldtrk", HasTSXLDTRK)
.Case("uintr", HasUINTR)
+ .Case("usermsr", HasUSERMSR)
.Case("vaes", HasVAES)
.Case("vpclmulqdq", HasVPCLMULQDQ)
.Case("wbnoinvd", HasWBNOINVD)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index 4fdc94de1e0cb4d..298db55c67442c9 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -162,6 +162,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasAMXCOMPLEX = false;
bool HasSERIALIZE = false;
bool HasTSXLDTRK = false;
+ bool HasUSERMSR = false;
bool HasUINTR = false;
bool HasCRC32 = false;
bool HasX87 = false;
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 8deea823e396694..3b6fec3da2b16ff 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -224,6 +224,7 @@ set(x86_files
tmmintrin.h
tsxldtrkintrin.h
uintrintrin.h
+ usermsrintrin.h
vaesintrin.h
vpclmulqdqintrin.h
waitpkgintrin.h
diff --git a/clang/lib/Headers/usermsrintrin.h b/clang/lib/Headers/usermsrintrin.h
new file mode 100644
index 000000000000000..6d1424ad3b2edd7
--- /dev/null
+++ b/clang/lib/Headers/usermsrintrin.h
@@ -0,0 +1,30 @@
+/*===--------------- usermsrintrin.h - USERMSR intrinsics -----------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+#ifndef __X86GPRINTRIN_H
+#error "Never use <usermsrintrin.h> directly; include <x86gprintrin.h> instead."
+#endif // __X86GPRINTRIN_H
+
+#ifndef __USERMSRINTRIN_H
+#define __USERMSRINTRIN_H
+#ifdef __x86_64__
+
+static __inline__ unsigned long long
+ __attribute__((__always_inline__, __nodebug__, __target__("usermsr")))
+ _urdmsr(unsigned long long __A) {
+ return __builtin_ia32_urdmsr(__A);
+}
+
+static __inline__ void
+ __attribute__((__always_inline__, __nodebug__, __target__("usermsr")))
+ _uwrmsr(unsigned long long __A, unsigned long long __B) {
+ return __builtin_ia32_uwrmsr(__A, __B);
+}
+
+#endif // __x86_64__
+#endif // __USERMSRINTRIN_H
diff --git a/clang/lib/Headers/x86gprintrin.h b/clang/lib/Headers/x86gprintrin.h
index f9a765be432219b..1bdaad7dba279f6 100644
--- a/clang/lib/Headers/x86gprintrin.h
+++ b/clang/lib/Headers/x86gprintrin.h
@@ -20,6 +20,11 @@
#include <uintrintrin.h>
#endif
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
+ defined(__UINTR__)
+#include <usermsrintrin.h>
+#endif
+
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
defined(__CRC32__)
#include <crc32intrin.h>
diff --git a/clang/test/CodeGen/X86/usermsr-builtins-error-32.c b/clang/test/CodeGen/X86/usermsr-builtins-error-32.c
new file mode 100644
index 000000000000000..5b3c8d00a46f68f
--- /dev/null
+++ b/clang/test/CodeGen/X86/usermsr-builtins-error-32.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +usermsr \
+// RUN: -emit-llvm -fsyntax-only -verify
+
+#include <immintrin.h>
+
+unsigned long long test_urdmsr(unsigned long long __A) {
+ return _urdmsr(__A); // expected-error {{call to undeclared function '_urdmsr'}}
+}
+
+void test_uwrmsr(unsigned long long __A, unsigned long long __B) {
+ // CHECK-LABEL: @test_uwrmsr(
+ // CHECK: call void @llvm.x86.uwrmsr(
+ _uwrmsr(__A, __B); // expected-error {{call to undeclared function '_uwrmsr'}}
+}
diff --git a/clang/test/CodeGen/X86/usermsr-builtins.c b/clang/test/CodeGen/X86/usermsr-builtins.c
new file mode 100644
index 000000000000000..4ca68f4f35f2ac0
--- /dev/null
+++ b/clang/test/CodeGen/X86/usermsr-builtins.c
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +usermsr \
+// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s
+
+#include <immintrin.h>
+
+unsigned long long test_urdmsr(unsigned long long __A) {
+ // CHECK-LABEL: @test_urdmsr(
+ // CHECK: call i64 @llvm.x86.urdmsr(
+ return _urdmsr(__A);
+}
+
+unsigned long long test_urdmsr_const(unsigned long long __A) {
+ // CHECK-LABEL: @test_urdmsr_const(
+ // CHECK: call i64 @llvm.x86.urdmsr(
+ return _urdmsr(123u);
+}
+
+void test_uwrmsr(unsigned long long __A, unsigned long long __B) {
+ // CHECK-LABEL: @test_uwrmsr(
+ // CHECK: call void @llvm.x86.uwrmsr(
+ _uwrmsr(__A, __B);
+}
+
+void test_uwrmsr_const(unsigned long long __A, unsigned long long __B) {
+ // CHECK-LABEL: @test_uwrmsr_const(
+ // CHECK: call void @llvm.x86.uwrmsr(
+ _uwrmsr(123u, __B);
+}
+
diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c
index a6ecedbb8a58e7b..464dcda504bbdc3 100644
--- a/clang/test/Driver/x86-target-features.c
+++ b/clang/test/Driver/x86-target-features.c
@@ -374,6 +374,11 @@
// EVEX512: "-target-feature" "+evex512"
// NO-EVEX512: "-target-feature" "-evex512"
+// RUN: %clang --target=i386 -musermsr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=USERMSR %s
+// RUN: %clang --target=i386 -mno-usermsr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-USERMSR %s
+// USERMSR: "-target-feature" "+usermsr"
+// NO-USERMSR: "-target-feature" "-usermsr"
+
// RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
// RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
// CRC32: "-target-feature" "+crc32"
diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c
index 36d4af59d4c66f6..873416d79b1255c 100644
--- a/clang/test/Preprocessor/x86_target_features.c
+++ b/clang/test/Preprocessor/x86_target_features.c
@@ -750,6 +750,12 @@
// AVXVNNIINT16NOAVX2-NOT: #define __AVX2__ 1
// AVXVNNIINT16NOAVX2-NOT: #define __AVXVNNIINT16__ 1
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -musermsr -x c -E -dM -o - %s | FileCheck -check-prefix=USERMSR %s
+// USERMSR: #define __USERMSR__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-usermsr -x c -E -dM -o - %s | FileCheck -check-prefix=NO-USERMSR %s
+// NO-USERMSR-NOT: #define __USERMSR__ 1
+
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
// CRC32: #define __CRC32__ 1
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 103c08ffbe83b38..364342f20cf8215 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -922,8 +922,6 @@ endif()
include(HandleLLVMOptions)
-######
-
# Configure all of the various header file fragments LLVM uses which depend on
# configuration variables.
set(LLVM_ENUM_TARGETS "")
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 3453c7e61ae4a63..3d11c43052f322d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -133,6 +133,7 @@ Changes to the X86 Backend
benefits external projects such as Rust which aim to be binary compatible
with C, but also fixes code generation where LLVM already assumed that the
type matched and called into libgcc helper functions.
+* Support ISA of ``USER_MSR``.
Changes to the OCaml bindings
-----------------------------
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 57cd1dc47bd9fc9..fdc2b0fb7f80f12 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5673,8 +5673,16 @@ let TargetPrefix = "x86" in {
Intrinsic<[], [llvm_i64_ty], []>;
}
+let TargetPrefix = "x86" in {
+def int_x86_urdmsr : ClangBuiltin<"__builtin_ia32_urdmsr">,
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty],
+ [IntrInaccessibleMemOnly]>;
+def int_x86_uwrmsr : ClangBuiltin<"__builtin_ia32_uwrmsr">,
+ Intrinsic<[], [llvm_i64_ty, llvm_i64_ty],
+ [IntrInaccessibleMemOnly]>;
+}
+
//===----------------------------------------------------------------------===//
-// avx512_fp16: vaddph
let TargetPrefix = "x86" in {
def int_x86_avx512fp16_add_ph_512
: ClangBuiltin<"__builtin_ia32_addph512">,
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 169b8e97986e154..6e08fc6a0ccb650 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -33,6 +33,7 @@ namespace X86Disassembler {
#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
#define MAP5_SYM x86DisassemblerMap5Opcodes
#define MAP6_SYM x86DisassemblerMap6Opcodes
+#define MAP7_SYM x86DisassemblerMap7Opcodes
#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
#define CONTEXTS_STR "x86DisassemblerContexts"
@@ -46,6 +47,7 @@ namespace X86Disassembler {
#define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
#define MAP5_STR "x86DisassemblerMap5Opcodes"
#define MAP6_STR "x86DisassemblerMap6Opcodes"
+#define MAP7_STR "x86DisassemblerMap7Opcodes"
// Attributes of an instruction that must be known before the opcode can be
// processed correctly. Most of these indicate the presence of particular
@@ -296,7 +298,8 @@ enum OpcodeType {
XOPA_MAP = 6,
THREEDNOW_MAP = 7,
MAP5 = 8,
- MAP6 = 9
+ MAP6 = 9,
+ MAP7 = 10
};
// The following structs are used for the hierarchical decode table. After
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 85ff6996d335ae7..7505444313d4a01 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -241,6 +241,7 @@ X86_FEATURE (SM3, "sm3")
X86_FEATURE (SM4, "sm4")
X86_FEATURE (AVXVNNIINT16, "avxvnniint16")
X86_FEATURE (EVEX512, "evex512")
+X86_FEATURE (USERMSR, "usermsr")
// These features aren't really CPU features, but the frontend can set them.
X86_FEATURE (RETPOLINE_EXTERNAL_THUNK, "retpoline-external-thunk")
X86_FEATURE (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 49651da63ecf966..0678a5a11d9f730 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -156,6 +156,9 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext,
case MAP6:
dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
+ case MAP7:
+ dec = &MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
+ break;
}
switch (dec->modrm_type) {
@@ -918,6 +921,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
case VEX_LOB_MAP6:
insn->opcodeType = MAP6;
return consume(insn, insn->opcode);
+ case VEX_LOB_MAP7:
+ insn->opcodeType = MAP7;
+ return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_2B) {
insn->opcodeType = TWOBYTE;
@@ -1059,6 +1065,9 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID,
case MAP6:
decision = &MAP6_SYM;
break;
+ case MAP7:
+ decision = &MAP7_SYM;
+ break;
}
if (decision->opcodeDecisions[insnCtx]
diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
index 95d3c8ede366f96..2d728143d3c9aa4 100644
--- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
+++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
@@ -484,7 +484,8 @@ enum VEXLeadingOpcodeByte {
VEX_LOB_0F38 = 0x2,
VEX_LOB_0F3A = 0x3,
VEX_LOB_MAP5 = 0x5,
- VEX_LOB_MAP6 = 0x6
+ VEX_LOB_MAP6 = 0x6,
+ VEX_LOB_MAP7 = 0x7
};
enum XOPMapSelect {
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index e2293fe30561fb4..1e5a3606f33a6fc 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -829,9 +829,10 @@ namespace X86II {
/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
ThreeDNow = 7 << OpMapShift,
- // MAP5, MAP6 - Prefix after the 0x0F prefix.
+ // MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
T_MAP5 = 8 << OpMapShift,
T_MAP6 = 9 << OpMapShift,
+ T_MAP7 = 10 << OpMapShift,
//===------------------------------------------------------------------===//
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 59a04f3167d863c..b85404be3063dae 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -89,6 +89,7 @@ class X86OpcodePrefixHelper {
// 0b00100: Reserved for future use
// 0b00101: VEX MAP5
// 0b00110: VEX MAP6
+ // 0b00111: VEX MAP7
// 0b00111-0b11111: Reserved for future use
// 0b01000: XOP map select - 08h instructions with imm byte
// 0b01001: XOP map select - 09h instructions with no imm byte
@@ -917,6 +918,9 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
case X86II::T_MAP6:
Prefix.set5M(0x6);
break;
+ case X86II::T_MAP7:
+ Prefix.set5M(0x7);
+ break;
}
Prefix.setL(TSFlags & X86II::VEX_L);
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 64f91ae90e2b0ce..0b9a2e8acf9e10b 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -325,6 +325,8 @@ def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",
"Support TSXLDTRK instructions">;
def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
"Has UINTR Instructions">;
+def FeatureUSERMSR : SubtargetFeature<"usermsr", "HasUSERMSR", "true",
+ "Support USERMSR instructions">;
def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
"platform configuration instruction">;
def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index f45869e15267c89..70ffd4175e1f145 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -163,6 +163,7 @@ def XOPA : Map<6>;
def ThreeDNow : Map<7>;
def T_MAP5 : Map<8>;
def T_MAP6 : Map<9>;
+def T_MAP7 : Map<10>;
// Class specifying the encoding
class Encoding<bits<2> val> {
@@ -217,6 +218,9 @@ class T_MAP6PS : T_MAP6 { Prefix OpPrefix = PS; }
class T_MAP6PD : T_MAP6 { Prefix OpPrefix = PD; }
class T_MAP6XS : T_MAP6 { Prefix OpPrefix = XS; }
class T_MAP6XD : T_MAP6 { Prefix OpPrefix = XD; }
+class T_MAP7 { Map OpMap = T_MAP7; }
+class T_MAP7XS : T_MAP7 { Prefix OpPrefix = XS; } // 0xF3
+class T_MAP7XD : T_MAP7 { Prefix OpPrefix = XD; } // 0xF2
class OBXS { Prefix OpPrefix = XS; }
class PS : TB { Prefix OpPrefix = PS; }
class PD : TB { Prefix OpPrefix = PD; }
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index a20fa6a0c3b6c63..cb740bc99f7884c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -1017,6 +1017,7 @@ def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">;
def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">;
def HasAMXCOMPLEX : Predicate<"Subtarget->hasAMXCOMPLEX()">;
def HasUINTR : Predicate<"Subtarget->hasUINTR()">;
+def HasUSERMSR : Predicate<"Subtarget->hasUSERMSR()">;
def HasCRC32 : Predicate<"Subtarget->hasCRC32()">;
def HasX86_64 : Predicate<"Subtarget->hasX86_64()">;
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 0272f7de0f9e4b5..b55956169ff2cfe 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,6 +436,22 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, XD;
}
+let Predicates = [HasUSERMSR], mayLoad = 1 in {
+ def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+ "urdmsr\t{$src, $dst|$dst, $src}",
+ [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8XD;
+ def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "urdmsr\t{$imm, $dst|$dst, $imm}...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff a712244f3b76cd2ef60b4f3ce5efaf6d4d49c6fe cfc302a80583548815cbf725a8576edbc7731dfc -- clang/lib/Headers/usermsrintrin.h clang/test/CodeGen/X86/usermsr-builtins-error-32.c clang/test/CodeGen/X86/usermsr-builtins.c clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Headers/x86gprintrin.h clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/utils/TableGen/X86DisassemblerTables.cpp llvm/utils/TableGen/X86DisassemblerTables.h llvm/utils/TableGen/X86RecognizableInstr.cpp llvm/utils/TableGen/X86RecognizableInstr.hView the diff from clang-format here.diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 6e08fc6a0ccb..82419fb80cdf 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -33,7 +33,7 @@ namespace X86Disassembler {
#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
#define MAP5_SYM x86DisassemblerMap5Opcodes
#define MAP6_SYM x86DisassemblerMap6Opcodes
-#define MAP7_SYM x86DisassemblerMap7Opcodes
+#define MAP7_SYM x86DisassemblerMap7Opcodes
#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
#define CONTEXTS_STR "x86DisassemblerContexts"
@@ -47,7 +47,7 @@ namespace X86Disassembler {
#define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
#define MAP5_STR "x86DisassemblerMap5Opcodes"
#define MAP6_STR "x86DisassemblerMap6Opcodes"
-#define MAP7_STR "x86DisassemblerMap7Opcodes"
+#define MAP7_STR "x86DisassemblerMap7Opcodes"
// Attributes of an instruction that must be known before the opcode can be
// processed correctly. Most of these indicate the presence of particular
@@ -289,17 +289,17 @@ enum InstructionContext {
// Opcode types, which determine which decode table to use, both in the Intel
// manual and also for the decoder.
enum OpcodeType {
- ONEBYTE = 0,
- TWOBYTE = 1,
- THREEBYTE_38 = 2,
- THREEBYTE_3A = 3,
- XOP8_MAP = 4,
- XOP9_MAP = 5,
- XOPA_MAP = 6,
+ ONEBYTE = 0,
+ TWOBYTE = 1,
+ THREEBYTE_38 = 2,
+ THREEBYTE_3A = 3,
+ XOP8_MAP = 4,
+ XOP9_MAP = 5,
+ XOPA_MAP = 6,
THREEDNOW_MAP = 7,
- MAP5 = 8,
- MAP6 = 9,
- MAP7 = 10
+ MAP5 = 8,
+ MAP6 = 9,
+ MAP7 = 10
};
// The following structs are used for the hierarchical decode table. After
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index 1e5a3606f33a..07eaad70c612 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -584,32 +584,32 @@ namespace X86II {
// PseudoFrm - This represents an instruction that is a pseudo instruction
// or one that has not been implemented yet. It is illegal to code generate
// it, but tolerated for intermediate implementation stages.
- Pseudo = 0,
+ Pseudo = 0,
/// Raw - This form is for instructions that don't have any operands, so
/// they are just a fixed opcode value, like 'leave'.
- RawFrm = 1,
+ RawFrm = 1,
/// AddRegFrm - This form is used for instructions like 'push r32' that have
/// their one register operand added to their opcode.
- AddRegFrm = 2,
+ AddRegFrm = 2,
/// RawFrmMemOffs - This form is for instructions that store an absolute
/// memory offset as an immediate with a possible segment override.
- RawFrmMemOffs = 3,
+ RawFrmMemOffs = 3,
/// RawFrmSrc - This form is for instructions that use the source index
/// register SI/ESI/RSI with a possible segment override.
- RawFrmSrc = 4,
+ RawFrmSrc = 4,
/// RawFrmDst - This form is for instructions that use the destination index
/// register DI/EDI/RDI.
- RawFrmDst = 5,
+ RawFrmDst = 5,
/// RawFrmDstSrc - This form is for instructions that use the source index
/// register SI/ESI/RSI with a possible segment override, and also the
/// destination index register DI/EDI/RDI.
- RawFrmDstSrc = 6,
+ RawFrmDstSrc = 6,
/// RawFrmImm8 - This is used for the ENTER instruction, which has two
/// immediates, the first of which is a 16-bit immediate (specified by
@@ -630,7 +630,8 @@ namespace X86II {
/// byte like data16 or rep.
PrefixByte = 10,
- /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
+ /// MRMDestMem4VOp3CC - This form is used for instructions that use the
+ /// Mod/RM
/// byte to specify a destination which in this case is memory and operand 3
/// with VEX.VVVV, and also encodes a condition code.
MRMDestMem4VOp3CC = 20,
@@ -644,7 +645,7 @@ namespace X86II {
MRMr0 = 21,
/// MRMSrcMem - But force to use the SIB field.
- MRMSrcMemFSIB = 22,
+ MRMSrcMemFSIB = 22,
/// MRMDestMem - But force to use the SIB field.
MRMDestMemFSIB = 23,
@@ -652,12 +653,12 @@ namespace X86II {
/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
/// to specify a destination, which in this case is memory.
///
- MRMDestMem = 24,
+ MRMDestMem = 24,
/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
/// to specify a source, which in this case is memory.
///
- MRMSrcMem = 25,
+ MRMSrcMem = 25,
/// MRMSrcMem4VOp3 - This form is used for instructions that encode
/// operand 3 with VEX.VVVV and load from memory.
@@ -667,12 +668,12 @@ namespace X86II {
/// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
/// byte to specify the fourth source, which in this case is memory.
///
- MRMSrcMemOp4 = 27,
+ MRMSrcMemOp4 = 27,
/// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
/// byte to specify the operands and also encodes a condition code.
///
- MRMSrcMemCC = 28,
+ MRMSrcMemCC = 28,
/// MRMXm - This form is used for instructions that use the Mod/RM byte
/// to specify a memory source, but doesn't use the middle field. And has
@@ -686,18 +687,24 @@ namespace X86II {
MRMXm = 31,
// Next, instructions that operate on a memory r/m operand...
- MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, // Format /0 /1 /2 /3
- MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, // Format /4 /5 /6 /7
+ MRM0m = 32,
+ MRM1m = 33,
+ MRM2m = 34,
+ MRM3m = 35, // Format /0 /1 /2 /3
+ MRM4m = 36,
+ MRM5m = 37,
+ MRM6m = 38,
+ MRM7m = 39, // Format /4 /5 /6 /7
/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
/// to specify a destination, which in this case is a register.
///
- MRMDestReg = 40,
+ MRMDestReg = 40,
/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
/// to specify a source, which in this case is a register.
///
- MRMSrcReg = 41,
+ MRMSrcReg = 41,
/// MRMSrcReg4VOp3 - This form is used for instructions that encode
/// operand 3 with VEX.VVVV and do not load from memory.
@@ -707,12 +714,12 @@ namespace X86II {
/// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
/// byte to specify the fourth source, which in this case is a register.
///
- MRMSrcRegOp4 = 43,
+ MRMSrcRegOp4 = 43,
/// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
/// byte to specify the operands and also encodes a condition code
///
- MRMSrcRegCC = 44,
+ MRMSrcRegCC = 44,
/// MRMXCCr - This form is used for instructions that use the Mod/RM byte
/// to specify a register source, but doesn't use the middle field. And has
@@ -726,32 +733,92 @@ namespace X86II {
MRMXr = 47,
// Instructions that operate on a register r/m operand...
- MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3
- MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7
+ MRM0r = 48,
+ MRM1r = 49,
+ MRM2r = 50,
+ MRM3r = 51, // Format /0 /1 /2 /3
+ MRM4r = 52,
+ MRM5r = 53,
+ MRM6r = 54,
+ MRM7r = 55, // Format /4 /5 /6 /7
// Instructions that operate that have mod=11 and an opcode but ignore r/m.
- MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, // Format /0 /1 /2 /3
- MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, // Format /4 /5 /6 /7
+ MRM0X = 56,
+ MRM1X = 57,
+ MRM2X = 58,
+ MRM3X = 59, // Format /0 /1 /2 /3
+ MRM4X = 60,
+ MRM5X = 61,
+ MRM6X = 62,
+ MRM7X = 63, // Format /4 /5 /6 /7
/// MRM_XX - A mod/rm byte of exactly 0xXX.
- MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
- MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
- MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
- MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
- MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
- MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
- MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
- MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
- MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
- MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
- MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
- MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
- MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
- MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
- MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
- MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
-
- FormMask = 127,
+ MRM_C0 = 64,
+ MRM_C1 = 65,
+ MRM_C2 = 66,
+ MRM_C3 = 67,
+ MRM_C4 = 68,
+ MRM_C5 = 69,
+ MRM_C6 = 70,
+ MRM_C7 = 71,
+ MRM_C8 = 72,
+ MRM_C9 = 73,
+ MRM_CA = 74,
+ MRM_CB = 75,
+ MRM_CC = 76,
+ MRM_CD = 77,
+ MRM_CE = 78,
+ MRM_CF = 79,
+ MRM_D0 = 80,
+ MRM_D1 = 81,
+ MRM_D2 = 82,
+ MRM_D3 = 83,
+ MRM_D4 = 84,
+ MRM_D5 = 85,
+ MRM_D6 = 86,
+ MRM_D7 = 87,
+ MRM_D8 = 88,
+ MRM_D9 = 89,
+ MRM_DA = 90,
+ MRM_DB = 91,
+ MRM_DC = 92,
+ MRM_DD = 93,
+ MRM_DE = 94,
+ MRM_DF = 95,
+ MRM_E0 = 96,
+ MRM_E1 = 97,
+ MRM_E2 = 98,
+ MRM_E3 = 99,
+ MRM_E4 = 100,
+ MRM_E5 = 101,
+ MRM_E6 = 102,
+ MRM_E7 = 103,
+ MRM_E8 = 104,
+ MRM_E9 = 105,
+ MRM_EA = 106,
+ MRM_EB = 107,
+ MRM_EC = 108,
+ MRM_ED = 109,
+ MRM_EE = 110,
+ MRM_EF = 111,
+ MRM_F0 = 112,
+ MRM_F1 = 113,
+ MRM_F2 = 114,
+ MRM_F3 = 115,
+ MRM_F4 = 116,
+ MRM_F5 = 117,
+ MRM_F6 = 118,
+ MRM_F7 = 119,
+ MRM_F8 = 120,
+ MRM_F9 = 121,
+ MRM_FA = 122,
+ MRM_FB = 123,
+ MRM_FC = 124,
+ MRM_FD = 125,
+ MRM_FE = 126,
+ MRM_FF = 127,
+
+ FormMask = 127,
//===------------------------------------------------------------------===//
// Actual flags...
@@ -763,18 +830,18 @@ namespace X86II {
OpSizeShift = 7,
OpSizeMask = 0x3 << OpSizeShift,
- OpSizeFixed = 0 << OpSizeShift,
- OpSize16 = 1 << OpSizeShift,
- OpSize32 = 2 << OpSizeShift,
+ OpSizeFixed = 0 << OpSizeShift,
+ OpSize16 = 1 << OpSizeShift,
+ OpSize32 = 2 << OpSizeShift,
// AsSize - AdSizeX implies this instruction determines its need of 0x67
// prefix from a normal ModRM memory operand. The other types indicate that
// an operand is encoded with a specific width and a prefix is needed if
// it differs from the current mode.
AdSizeShift = OpSizeShift + 2,
- AdSizeMask = 0x3 << AdSizeShift,
+ AdSizeMask = 0x3 << AdSizeShift,
- AdSizeX = 0 << AdSizeShift,
+ AdSizeX = 0 << AdSizeShift,
AdSize16 = 1 << AdSizeShift,
AdSize32 = 2 << AdSizeShift,
AdSize64 = 3 << AdSizeShift,
@@ -785,7 +852,7 @@ namespace X86II {
// no prefix.
//
OpPrefixShift = AdSizeShift + 2,
- OpPrefixMask = 0x3 << OpPrefixShift,
+ OpPrefixMask = 0x3 << OpPrefixShift,
// PD - Prefix code for packed double precision vector floating point
// operations performed in the SSE registers.
@@ -793,14 +860,15 @@ namespace X86II {
// XS, XD - These prefix codes are for single and double precision scalar
// floating point operations performed in the SSE registers.
- XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift,
+ XS = 2 << OpPrefixShift,
+ XD = 3 << OpPrefixShift,
//===------------------------------------------------------------------===//
// OpMap - This field determines which opcode map this instruction
// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
//
OpMapShift = OpPrefixShift + 2,
- OpMapMask = 0xF << OpMapShift,
+ OpMapMask = 0xF << OpMapShift,
// OB - OneByte - Set if this instruction has a one byte opcode.
OB = 0 << OpMapShift,
@@ -810,7 +878,8 @@ namespace X86II {
TB = 1 << OpMapShift,
// T8, TA - Prefix after the 0x0F prefix.
- T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
+ T8 = 2 << OpMapShift,
+ TA = 3 << OpMapShift,
// XOP8 - Prefix to include use of imm byte.
XOP8 = 4 << OpMapShift,
@@ -840,39 +909,39 @@ namespace X86II {
// etc. We only cares about REX.W and REX.R bits and only the former is
// statically determined.
//
- REXShift = OpMapShift + 4,
- REX_W = 1 << REXShift,
+ REXShift = OpMapShift + 4,
+ REX_W = 1 << REXShift,
//===------------------------------------------------------------------===//
// This three-bit field describes the size of an immediate operand. Zero is
// unused so that we can tell if we forgot to set a value.
ImmShift = REXShift + 1,
- ImmMask = 15 << ImmShift,
- Imm8 = 1 << ImmShift,
- Imm8PCRel = 2 << ImmShift,
- Imm8Reg = 3 << ImmShift,
- Imm16 = 4 << ImmShift,
+ ImmMask = 15 << ImmShift,
+ Imm8 = 1 << ImmShift,
+ Imm8PCRel = 2 << ImmShift,
+ Imm8Reg = 3 << ImmShift,
+ Imm16 = 4 << ImmShift,
Imm16PCRel = 5 << ImmShift,
- Imm32 = 6 << ImmShift,
+ Imm32 = 6 << ImmShift,
Imm32PCRel = 7 << ImmShift,
- Imm32S = 8 << ImmShift,
- Imm64 = 9 << ImmShift,
+ Imm32S = 8 << ImmShift,
+ Imm64 = 9 << ImmShift,
//===------------------------------------------------------------------===//
// FP Instruction Classification... Zero is non-fp instruction.
// FPTypeMask - Mask for all of the FP types...
FPTypeShift = ImmShift + 4,
- FPTypeMask = 7 << FPTypeShift,
+ FPTypeMask = 7 << FPTypeShift,
// NotFP - The default, set for instructions that do not use FP registers.
- NotFP = 0 << FPTypeShift,
+ NotFP = 0 << FPTypeShift,
// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
- ZeroArgFP = 1 << FPTypeShift,
+ ZeroArgFP = 1 << FPTypeShift,
// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
- OneArgFP = 2 << FPTypeShift,
+ OneArgFP = 2 << FPTypeShift,
// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
// result back to ST(0). For example, fcos, fsqrt, etc.
@@ -882,17 +951,17 @@ namespace X86II {
// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
// explicit argument, storing the result to either ST(0) or the implicit
// argument. For example: fadd, fsub, fmul, etc...
- TwoArgFP = 4 << FPTypeShift,
+ TwoArgFP = 4 << FPTypeShift,
// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
// explicit argument, but have no destination. Example: fucom, fucomi, ...
- CompareFP = 5 << FPTypeShift,
+ CompareFP = 5 << FPTypeShift,
// CondMovFP - "2 operand" floating point conditional move instructions.
- CondMovFP = 6 << FPTypeShift,
+ CondMovFP = 6 << FPTypeShift,
// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
- SpecialFP = 7 << FPTypeShift,
+ SpecialFP = 7 << FPTypeShift,
// Lock prefix
LOCKShift = FPTypeShift + 3,
@@ -923,36 +992,36 @@ namespace X86II {
EVEX = 3 << EncodingShift,
// Opcode
- OpcodeShift = EncodingShift + 2,
+ OpcodeShift = EncodingShift + 2,
/// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
/// address instructions in SSE are represented as 3 address ones in AVX
/// and the additional register is encoded in VEX_VVVV prefix.
VEX_4VShift = OpcodeShift + 8,
- VEX_4V = 1ULL << VEX_4VShift,
+ VEX_4V = 1ULL << VEX_4VShift,
/// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
/// instruction uses 256-bit wide registers. This is usually auto detected
/// if a VR256 register is used, but some AVX instructions also have this
/// field marked when using a f256 memory references.
VEX_LShift = VEX_4VShift + 1,
- VEX_L = 1ULL << VEX_LShift,
+ VEX_L = 1ULL << VEX_LShift,
// EVEX_K - Set if this instruction requires masking
EVEX_KShift = VEX_LShift + 1,
- EVEX_K = 1ULL << EVEX_KShift,
+ EVEX_K = 1ULL << EVEX_KShift,
// EVEX_Z - Set if this instruction has EVEX.Z field set.
EVEX_ZShift = EVEX_KShift + 1,
- EVEX_Z = 1ULL << EVEX_ZShift,
+ EVEX_Z = 1ULL << EVEX_ZShift,
// EVEX_L2 - Set if this instruction has EVEX.L' field set.
EVEX_L2Shift = EVEX_ZShift + 1,
- EVEX_L2 = 1ULL << EVEX_L2Shift,
+ EVEX_L2 = 1ULL << EVEX_L2Shift,
// EVEX_B - Set if this instruction has EVEX.B field set.
EVEX_BShift = EVEX_L2Shift + 1,
- EVEX_B = 1ULL << EVEX_BShift,
+ EVEX_B = 1ULL << EVEX_BShift,
// The scaling factor for the AVX512's 8-bit compressed displacement.
CD8_Scale_Shift = EVEX_BShift + 1,
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index b320911d3ce2..1f7e28cdbe2e 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1796,7 +1796,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
- Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
+ Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
bool HasLeafD = MaxLevel >= 0xd &&
!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 962da623b1ca..d4966bce9899 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -791,7 +791,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
case X86Local::T_MAP5: opcodeType = MAP5; break;
case X86Local::T_MAP6: opcodeType = MAP6; break;
- case X86Local::T_MAP7: opcodeType = MAP7; break;
+ case X86Local::T_MAP7:
+ opcodeType = MAP7;
+ break;
}
std::unique_ptr<ModRMFilter> filter;
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index 38bca87bfe61..a3222dc5f16b 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -136,8 +136,17 @@ namespace X86Local {
};
enum {
- OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7,
- T_MAP5 = 8, T_MAP6 = 9, T_MAP7 = 10
+ OB = 0,
+ TB = 1,
+ T8 = 2,
+ TA = 3,
+ XOP8 = 4,
+ XOP9 = 5,
+ XOPA = 6,
+ ThreeDNow = 7,
+ T_MAP5 = 8,
+ T_MAP6 = 9,
+ T_MAP7 = 10
};
enum {
|
phoebewang
reviewed
Oct 13, 2023
phoebewang
reviewed
Oct 13, 2023
phoebewang
reviewed
Oct 13, 2023
phoebewang
reviewed
Oct 13, 2023
phoebewang
reviewed
Oct 13, 2023
phoebewang
approved these changes
Oct 16, 2023
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