[PowerPC] Optimize allocation of Conditional Register

[bzEq]

In a single BB, if we allocate different physical condition registers for different definitions of virtual registers, performance improvement can be observed for some workloads.

[nemanjai]

Can you outline the reason for the performance improvement? I wonder if perhaps it would be better to implement a flag to tell the register allocator to use a circular allocation order for a particular register class (or at least for a subset of a register class - i.e. volatile registers, etc.).

[bzEq]

Can you outline the reason for the performance improvement?

This is found in our internal workload where the loop is short and inside the loop body, two CR-logic instructions, very near in the body, are writing the same CR register(though different field). If we modify the allocation of CR registers manually, we got significant improvement in IPC and runtime, though this PR doesn't affect SPEC2017 too much.

I wonder if perhaps it would be better to implement a flag to tell the register allocator to use a circular allocation order for a particular register class

This is a good idea that worth a try. I'll investigate it.

[bzEq]

tell the register allocator to use a circular allocation order for a particular register class

I've got through the code of GreedyRA, this might not help a lot, since the order of allocating virtual registers is determined by priority, not the definition order inside one MBB. That's to say there is still possibility adjacent CR bit definition might be allocating the same CR even in circular allocation order.