[clang][RISCV] Enable RVV with function attribute attribute((target("arch=+v"))) #83674

4vtomat · 2024-03-02T14:23:27Z

It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:

#include <riscv_vector.h>

__attribute__((target("arch=+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
  return __riscv_vadd(v1, v2, vl);
}

int other_add(int i1, int i2) {
  return i1 + i2;
}

, it is supposed to be compilable even the vector is not specified, e.g.
clang -target riscv64 -march=rv64gc -S test.c.

llvmbot · 2024-03-02T14:23:54Z

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang

Author: Brandon Wu (4vtomat)

Changes

It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:

#include &lt;riscv_vector.h&gt;

__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
  return __riscv_vadd(v1, v2, vl);
}

int other_add(int i1, int i2) {
  return i1 + i2;
}

, it is supposed to be compilable even the vector is not specified, e.g.
clang -target riscv64 -march=rv64gc -S test.c.

Full diff: https://github.com/llvm/llvm-project/pull/83674.diff

10 Files Affected:

(modified) clang/include/clang/Sema/Sema.h (+2-1)
(modified) clang/lib/Basic/Targets/RISCV.cpp (+2-1)
(modified) clang/lib/Sema/Sema.cpp (+5-2)
(modified) clang/lib/Sema/SemaChecking.cpp (+9-61)
(modified) clang/lib/Sema/SemaDecl.cpp (+7-2)
(modified) clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c (+2-2)
(modified) clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c (+4-8)
(modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (+1-1)
(added) clang/test/Sema/riscv-function-target-attr.c (+41)
(modified) clang/utils/TableGen/RISCVVEmitter.cpp (-4)

diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
   bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
   bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
                                      CallExpr *TheCall);
-  void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+  void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+                           const llvm::StringMap<bool> &FeatureMap);
   bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
                                          unsigned BuiltinID, CallExpr *TheCall);
   bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
         Ret.Duplicate = "tune=";
 
       Ret.Tune = AttrString;
-    }
+    } else if (Feature.starts_with("+"))
+      Ret.Features.push_back(Feature.str());
   }
   return Ret;
 }
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
         targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
     }
 
-    if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
-      checkRVVTypeSupport(Ty, Loc, D);
+    if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+      llvm::StringMap<bool> CallerFeatureMap;
+      Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+      checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+    }
 
     // Don't allow SVE types in functions without a SVE target.
     if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo &TI, CallExpr *TheCall,
 bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
                                          unsigned BuiltinID,
                                          CallExpr *TheCall) {
-  // CodeGenFunction can also detect this, but this gives a better error
-  // message.
-  bool FeatureMissing = false;
-  SmallVector<StringRef> ReqFeatures;
-  StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',', -1, false);
-
-  // Check if each required feature is included
-  for (StringRef F : ReqFeatures) {
-    SmallVector<StringRef> ReqOpFeatures;
-    F.split(ReqOpFeatures, '|');
-
-    if (llvm::none_of(ReqOpFeatures,
-                      [&TI](StringRef OF) { return TI.hasFeature(OF); })) {
-      std::string FeatureStrs;
-      bool IsExtension = true;
-      for (StringRef OF : ReqOpFeatures) {
-        // If the feature is 64bit, alter the string so it will print better in
-        // the diagnostic.
-        if (OF == "64bit") {
-          assert(ReqOpFeatures.size() == 1 && "Expected '64bit' to be alone");
-          OF = "RV64";
-          IsExtension = false;
-        }
-        if (OF == "32bit") {
-          assert(ReqOpFeatures.size() == 1 && "Expected '32bit' to be alone");
-          OF = "RV32";
-          IsExtension = false;
-        }
-
-        // Convert features like "zbr" and "experimental-zbr" to "Zbr".
-        OF.consume_front("experimental-");
-        std::string FeatureStr = OF.str();
-        FeatureStr[0] = std::toupper(FeatureStr[0]);
-        // Combine strings.
-        FeatureStrs += FeatureStrs.empty() ? "" : ", ";
-        FeatureStrs += "'";
-        FeatureStrs += FeatureStr;
-        FeatureStrs += "'";
-      }
-      // Error message
-      FeatureMissing = true;
-      Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
-          << IsExtension
-          << TheCall->getSourceRange() << StringRef(FeatureStrs);
-    }
-  }
-
-  if (FeatureMissing)
-    return true;
-
   // vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx,
   // vsmul.vv, vsmul.vx are not included for EEW=64 in Zve64*.
   switch (BuiltinID) {
@@ -6369,9 +6318,8 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
   return false;
 }
 
-void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
-  const TargetInfo &TI = Context.getTargetInfo();
-
+void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+                               const llvm::StringMap<bool> &FeatureMap) {
   ASTContext::BuiltinVectorTypeInfo Info =
       Context.getBuiltinVectorTypeInfo(Ty->castAs<BuiltinType>());
   unsigned EltSize = Context.getTypeSize(Info.ElementType);
@@ -6380,24 +6328,24 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
   // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
   // least zve64x
   if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
-      !TI.hasFeature("zve64x"))
+      !FeatureMap.lookup("zve64x"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
-  else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
-           !TI.hasFeature("zvfhmin"))
+  else if (Info.ElementType->isFloat16Type() && !FeatureMap.lookup("zvfh") &&
+           !FeatureMap.lookup("zvfhmin"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D)
         << Ty << "zvfh or zvfhmin";
   else if (Info.ElementType->isBFloat16Type() &&
-           !TI.hasFeature("experimental-zvfbfmin"))
+           !FeatureMap.lookup("experimental-zvfbfmin"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfbfmin";
   else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
-           !TI.hasFeature("zve32f"))
+           !FeatureMap.lookup("zve32f"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
   else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
-           !TI.hasFeature("zve64d"))
+           !FeatureMap.lookup("zve64d"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
   // Given that caller already checked isRVVType() before calling this function,
   // if we don't have at least zve32x supported, then we need to emit error.
-  else if (!TI.hasFeature("zve32x"))
+  else if (!FeatureMap.lookup("zve32x"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32x";
 }
 
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 6289cf75e17413..c023120131a349 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8917,8 +8917,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
     }
   }
 
-  if (T->isRVVSizelessBuiltinType())
-    checkRVVTypeSupport(T, NewVD->getLocation(), cast<Decl>(CurContext));
+  if (T->isRVVSizelessBuiltinType() && isa<FunctionDecl>(CurContext)) {
+    const FunctionDecl *FD = cast<FunctionDecl>(CurContext);
+    llvm::StringMap<bool> CallerFeatureMap;
+    Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+    checkRVVTypeSupport(T, NewVD->getLocation(), cast<Decl>(CurContext),
+                        CallerFeatureMap);
+  }
 }
 
 /// Perform semantic checking on a newly-created variable
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
index ecf090a128aac7..bad68504fab055 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -verify %s -o -
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -S -verify %s -o -
 
 unsigned int orc_b_64(unsigned int a) {
-  return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires: 'RV64'}}
+  return __builtin_riscv_orc_b_64(a); // expected-error {{'__builtin_riscv_orc_b_64' needs target feature zbb,64bit}}
 }
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c
index d2e3e76043aef1..a256bf75b031c6 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c
@@ -1,14 +1,10 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -verify %s -o -
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -S -verify %s -o -
 
 #include <stdint.h>
 
-uint32_t zip(uint32_t rs1)
+uint32_t zip_unzip(uint32_t rs1)
 {
-  return __builtin_riscv_zip_32(rs1); // expected-error {{builtin requires: 'RV32'}}
-}
-
-uint32_t unzip(uint32_t rs1)
-{
-  return __builtin_riscv_unzip_32(rs1); // expected-error {{builtin requires: 'RV32'}}
+  (void)__builtin_riscv_zip_32(rs1); // expected-error {{'__builtin_riscv_zip_32' needs target feature zbkb,32bit}}
+  return __builtin_riscv_unzip_32(rs1); // expected-error {{'__builtin_riscv_unzip_32' needs target feature zbkb,32bit}}
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
index 6ec9b057997690..ecb6c5f2702577 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
@@ -11,7 +11,7 @@
 // CHECK-RV64V-NEXT:    ret i32 [[CONV]]
 //
 
-// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions: 'Zve32x'
+// CHECK-RV64-ERR: error: '__builtin_rvv_vsetvli' needs target feature zve32x
 
 int test() {
   return __builtin_rvv_vsetvli(1, 0, 0);
diff --git a/clang/test/Sema/riscv-function-target-attr.c b/clang/test/Sema/riscv-function-target-attr.c
new file mode 100644
index 00000000000000..470b141aa98d92
--- /dev/null
+++ b/clang/test/Sema/riscv-function-target-attr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+void test_builtin() {
+  __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_rvv_vsetvli' needs target feature zve32x}}
+}
+
+__attribute__((target("+zve32x")))
+void test_builtin_w_zve32x() {
+  __riscv_vsetvl_e8m8(1);
+}
+
+void test_rvv_i32_type() {
+  vint32m1_t v; // expected-error {{RISC-V type 'vint32m1_t' (aka '__rvv_int32m1_t') requires the 'zve32x' extension}}
+}
+
+__attribute__((target("+zve32x")))
+void test_rvv_i32_type_w_zve32x() {
+  vint32m1_t v;
+}
+
+void test_rvv_f32_type() {
+  vfloat32m1_t v; // expected-error {{RISC-V type 'vfloat32m1_t' (aka '__rvv_float32m1_t') requires the 'zve32f' extension}}
+}
+
+__attribute__((target("+zve32f")))
+void test_rvv_f32_type_w_zve32f() {
+  vfloat32m1_t v;
+}
+
+void test_rvv_f64_type() {
+  vfloat64m1_t v; // expected-error {{RISC-V type 'vfloat64m1_t' (aka '__rvv_float64m1_t') requires the 'zve64x' extension}}
+}
+
+__attribute__((target("+zve64d")))
+void test_rvv_f64_type_w_zve64d() {
+  vfloat64m1_t v;
+}
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 8513174c88bfc3..5e41ef9f9d2684 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -334,10 +334,6 @@ void RVVEmitter::createHeader(raw_ostream &OS) {
   OS << "#include <stdint.h>\n";
   OS << "#include <stddef.h>\n\n";
 
-  OS << "#ifndef __riscv_vector\n";
-  OS << "#error \"Vector intrinsics require the vector extension.\"\n";
-  OS << "#endif\n\n";
-
   OS << "#ifdef __cplusplus\n";
   OS << "extern \"C\" {\n";
   OS << "#endif\n\n";

4vtomat · 2024-03-02T14:29:34Z

Related request: riscv-non-isa/riscv-c-api-doc#69

clang/lib/Basic/Targets/RISCV.cpp

clang/test/Sema/riscv-function-target-attr.c

4vtomat · 2024-03-04T17:04:35Z

Move the test cases to existing files.

4vtomat · 2024-03-06T02:48:29Z

Rebase.

topperc · 2024-03-12T23:53:36Z

clang/lib/Sema/SemaDecl.cpp

+  if (T->isRVVSizelessBuiltinType() && isa<FunctionDecl>(CurContext)) {
+    const FunctionDecl *FD = cast<FunctionDecl>(CurContext);
+    llvm::StringMap<bool> CallerFeatureMap;
+    Context.getFunctionFeatureMap(CallerFeatureMap, FD);


Does this impact compile time if the RVV types are used many times in a function as they would be for intrinsic code?

Yes, it does.
With 10k RVV type declarations,
This pr's compile time is approximately 8 times slower than original one.(0.56 seconds vs 0.07 seconds on the server)

Mostly costed by llvm::RISCVISAInfo::parseFeatures in RISCVTargetInfo::initFeatureMap.

Would it make sense to store a Map<FunctionDecl *, StringMap<bool> in RISCVTargetInfo class so RISCVTargetInfo::initFeatureMap only builds the feature map one time per FunctionDecl?

But we don't have the FunctionDecl info in the RISCVTargetInfo::initFeatureMap call.

But we don't have the FunctionDecl info in the RISCVTargetInfo::initFeatureMap call.

What about keeping this map in ASTContext instead?

@4vtomat if the MCPU has a feature but the function explicitly disables it then I think we want the -

Why don't we just remove it from feature map?

But we don't have the FunctionDecl info in the RISCVTargetInfo::initFeatureMap call.

What about keeping this map in ASTContext instead?

I guess it might be a feasible solution, however the memory usage might increase since it has to keep the map for each function during the lifetime of the ASTContext.
@topperc Do you think we can do this? Or we can leave it in TODO until it becomes a problem in some real cases.

@4vtomat if the MCPU has a feature but the function explicitly disables it then I think we want the -

Why don't we just remove it from feature map?

We also need the negative extensions if the target attribute string is a complete arch, e.g. __attribute__((target="arch=rv64i"))), because any extensions from mcpu need to be turned off.

@lukel97 Got it, thanks!

topperc

LGTM

…et("arch=+v"))) It is currently not possible to use "RVV type" and "RVV intrinsics" if the "zve32x" is not enabled globally. However in some cases we may want to use them only in some functions, for instance: ``` #include <riscv_vector.h> __attribute__((target("+zve32x"))) vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) { return __riscv_vadd(v1, v2, vl); } int other_add(int i1, int i2) { return i1 + i2; } ``` , it is supposed to be compilable even the vector is not specified, e.g. `clang -target riscv64 -march=rv64gc -S test.c`.

…_((target("arch=+v")))

4vtomat · 2024-03-27T15:21:45Z

Rebase

camel-cdr · 2024-06-03T21:56:44Z

FYI, the example code you shown doesn't compile anymore: https://godbolt.org/z/ooTWEGejf

This feature is quite important, without it we can't compile in RVV by default in a lot of libraries, e.g. simdutf, flac, ...

4vtomat · 2024-06-04T18:05:10Z

FYI, the example code you shown doesn't compile anymore: https://godbolt.org/z/ooTWEGejf

This feature is quite important, without it we can't compile in RVV by default in a lot of libraries, e.g. simdutf, flac, ...

I guess it should be __attribute__((target("arch=+zve32x"))) rather then __attribute__((target("+zve32x"))), sorry for misleading in the description, let me fix it.
Btw, you can check the test case in this PR to see the correct usage.

camel-cdr · 2024-06-04T18:54:46Z

Ah, thanks, that works.

How can support for behavior be detected?
The intrinsic spec says:

The __riscv_v_intrinsic macro is the C macro to test the compiler's support for the RISC-V "V" extension intrinsics.
and recommends using:

#ifdef __riscv_v_intrinsic
#include <riscv_vector.h>
#endif /* __riscv_v_intrinsic */

But clang only defines __riscv_v_intrinsic when RVV is enabled by an march option, shouldn't it now always be enabled when it's possible to include <riscv_vector.h>?

llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" labels Mar 2, 2024

4vtomat requested review from topperc and BeMg March 2, 2024 14:23

4vtomat requested review from asb and kito-cheng March 2, 2024 14:24

4vtomat mentioned this pull request Mar 2, 2024

Using vector intrinsics with __attribute__((target("arch=+v"))) riscv-non-isa/riscv-c-api-doc#69

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BeMg reviewed Mar 4, 2024

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BeMg reviewed Mar 4, 2024

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4vtomat force-pushed the enable_attribute_target_riscv branch from 51c5233 to 34c59f3 Compare March 4, 2024 10:40

4vtomat changed the title ~~[clang][RISCV] Support function attribute __attribute__((target("+attr")))~~ [clang][RISCV] Enable RVV with function attribute __attribute__((target("+attr"))) Mar 4, 2024

4vtomat changed the title ~~[clang][RISCV] Enable RVV with function attribute __attribute__((target("+attr")))~~ [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) Mar 4, 2024

4vtomat force-pushed the enable_attribute_target_riscv branch from 0e924a1 to 70faceb Compare March 6, 2024 02:48

topperc reviewed Mar 12, 2024

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topperc requested review from AaronBallman and erichkeane March 20, 2024 17:30

topperc approved these changes Mar 26, 2024

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4vtomat added 3 commits March 27, 2024 08:16

fixup! [clang][RISCV] Enable RVV with function attribute __attribute_…

f1d1262

…_((target("arch=+v")))

fixup! [clang][RISCV] Enable RVV with function attribute __attribute_…

f4d33d9

…_((target("arch=+v")))

4vtomat force-pushed the enable_attribute_target_riscv branch from 70faceb to f4d33d9 Compare March 27, 2024 15:20

4vtomat requested a review from Endilll as a code owner March 27, 2024 15:20

4vtomat merged commit 13b653a into llvm:main Mar 27, 2024
3 of 4 checks passed

4vtomat deleted the enable_attribute_target_riscv branch March 27, 2024 15:22

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[clang][RISCV] Enable RVV with function attribute attribute((target("arch=+v"))) #83674

[clang][RISCV] Enable RVV with function attribute attribute((target("arch=+v"))) #83674

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camel-cdr commented Jun 4, 2024

[clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) #83674

[clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) #83674

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4vtomat commented Mar 27, 2024

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camel-cdr commented Jun 4, 2024

[clang][RISCV] Enable RVV with function attribute attribute((target("arch=+v"))) #83674

[clang][RISCV] Enable RVV with function attribute attribute((target("arch=+v"))) #83674

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