Manual configuration of FPGA through bitstream {where both FPGA fabric and bitstream are generated using OpenFPGA tool}

[chaitalisathe]

Hello! I am using Open FPGA tool flow to design FPGA fabric and verify fabric as shown on the OpenFPGA tool website.

My project has two parts- in the first part I am generating fabric using OpenFPGA tool and generate the bitstream for my design.
In the second part, I am making use of bitstream generated from part 1 to configure FPGA, run the simulation and record the outputs from FPGA.

When I use a full testbench script from tool, it automatically configures the FPGA with bitstream for User’s design (My own design).
#[https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/testbench/]

Could it be possible to configure the FPGA through prog_input manually using bitstream file generated by the tool?
When I generated the FPGA fabric, I found that there was no prog_input port to configure the FPGA.
I only found following input output ports.

module fpga_top(prog_clk,set,reset, clk,gfpga_pad_GPIO_PAD, ccff_head, ccff_tail);

It would be great if you could point to any documents or example scripts to configure the FPGA manually and run the verification.
I really appreciate your help.

[tangxifan]

@chaitalisathe Please check my answer in #1508 If it does answer questions, please let me know.

[chaitalisathe]

Hello @tangxifan, Yes. That is exactly I was looking for. Thank you.