Now port/wire names uses "__" to avoid collision FPGA global ports

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• The port and wire names are named with frequently used names as eFPGA ports, such as greset and prog_reset, This really limits the naming choices for eFPGA chip designers.

What does this pull request change?

This PR improves in the following aspects:

• Now port/wire names uses "__" to avoid collision, e.g., prog_reset --> __prog_reset__

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.