Reduce Peak Memory Usage of Fabric Bitstream Database

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• Bitstream generation of memory banks has very high peak memory usage.
  • For a K4N4 48x48 architecture, the peak memory usage is 3GB
  • For a K4N4 96x96 architecture, the peak memory usage is >20GB
    This will create issues for OpenFPGA to fit customers' computers, e.g., laptop

What does this pull request change?

This PR improves in the following aspects:

• Use encoded data when storing the BL/WL addresses in fabric bitstream database.
• This significantly reduces the memory usage
• For a K4N4 96x96 architecture, the peak memory usage is ~1.3GB
• Add test cases on large scale memory bank architecture to CI

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[tangxifan]

@tpagarani @taoli4rs @alain-rs

The peak memory overhead issue should be solved. I am going to merge it.

However, I pointed out a limitation in the data structure here.

I expect to have another engineer to work on this and solve the potential issue.