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[rv_plic] Work around sim/synth mismatch in Vivado #1364

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merged 1 commit into from Jan 17, 2020

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msfschaffner
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@msfschaffner msfschaffner commented Jan 17, 2020

This works around a simulation synthesis mismatch that can be observed in Vivado 2018.3 and 2019.2 (other versions have not been tested).

In particular, Vivado optimizes away the rv_plic_target module if the ternary statements are present within the two generate loops. The workaround consists of rewriting these MUX statements with bitwise ops and assign statements.

The issue has been reported to Xilinx:
https://forums.xilinx.com/t5/Synthesis/Simulation-Synthesis-Mismatch-with-Vivado-2018-3/m-p/1065923#M33849

Signed-off-by: Michael Schaffner msf@opentitan.org

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Note that this patch requires #1365 to go in first, so do not merge yet (and if you build locally, make sure you pick both patches).

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Lgtm with the added comment. Thanks a lot!

assign is_tree[pa] = (sel) ? is_tree[c1] : is_tree[c0];
assign id_tree[pa] = (sel) ? id_tree[c1] : id_tree[c0];
assign max_tree[pa] = (sel) ? max_tree[c1] : max_tree[c0];
assign is_tree[pa] = (sel & is_tree[c1]) | ((~sel) & is_tree[c0]);
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Can you add a comment here that this is to work around a vivado bug, and reference the issue number? The code looks otherwise quite strange.

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I am still waiting for access to the Xilinx portal (I had to create a new account). In the meantime, let me add an explanation and a reference to our github issue.

@msfschaffner msfschaffner force-pushed the plic-hotfix branch 2 times, most recently from 1f0984a to 7f49b61 Compare January 17, 2020 21:32
This works around a simulation synthesis mismatch that can be observed
in Vivado 2018.3 and 2019.2 (other versions have not been tested).

In particular, Vivado optimizes away the rv_plic_target module if the
ternary statements are present within the two generate loops. The
workaround consists of rewriting these MUX statements with bitwise ops
and assign statements.

The issue has been reported to Xilinx:
https://forums.xilinx.com/t5/Synthesis/Simulation-Synthesis-Mismatch-with-Vivado-2018-3/m-p/1065923#M33849

Signed-off-by: Michael Schaffner <msf@opentitan.org>
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Ok I have added a comment with a link to the Xilinx issue.

@msfschaffner msfschaffner merged commit 12d4811 into lowRISC:master Jan 17, 2020
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Tracking issue: #1355

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3 participants