-
Notifications
You must be signed in to change notification settings - Fork 709
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
[rv_plic] Work around sim/synth mismatch in Vivado #1364
Conversation
Note that this patch requires #1365 to go in first, so do not merge yet (and if you build locally, make sure you pick both patches). |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Lgtm with the added comment. Thanks a lot!
assign is_tree[pa] = (sel) ? is_tree[c1] : is_tree[c0]; | ||
assign id_tree[pa] = (sel) ? id_tree[c1] : id_tree[c0]; | ||
assign max_tree[pa] = (sel) ? max_tree[c1] : max_tree[c0]; | ||
assign is_tree[pa] = (sel & is_tree[c1]) | ((~sel) & is_tree[c0]); |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Can you add a comment here that this is to work around a vivado bug, and reference the issue number? The code looks otherwise quite strange.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I am still waiting for access to the Xilinx portal (I had to create a new account). In the meantime, let me add an explanation and a reference to our github issue.
1f0984a
to
7f49b61
Compare
This works around a simulation synthesis mismatch that can be observed in Vivado 2018.3 and 2019.2 (other versions have not been tested). In particular, Vivado optimizes away the rv_plic_target module if the ternary statements are present within the two generate loops. The workaround consists of rewriting these MUX statements with bitwise ops and assign statements. The issue has been reported to Xilinx: https://forums.xilinx.com/t5/Synthesis/Simulation-Synthesis-Mismatch-with-Vivado-2018-3/m-p/1065923#M33849 Signed-off-by: Michael Schaffner <msf@opentitan.org>
7f49b61
to
3e3c680
Compare
Ok I have added a comment with a link to the Xilinx issue. |
Tracking issue: #1355 |
This works around a simulation synthesis mismatch that can be observed in Vivado 2018.3 and 2019.2 (other versions have not been tested).
In particular, Vivado optimizes away the
rv_plic_target
module if the ternary statements are present within the two generate loops. The workaround consists of rewriting these MUX statements with bitwise ops and assign statements.The issue has been reported to Xilinx:
https://forums.xilinx.com/t5/Synthesis/Simulation-Synthesis-Mismatch-with-Vivado-2018-3/m-p/1065923#M33849
Signed-off-by: Michael Schaffner msf@opentitan.org