Signed-off-by: Robert Schilling <rschilling@rivosinc.com>

Signed-off-by: Michael Schaffner <msf@opentitan.org>

Signed-off-by: Michael Schaffner <msf@opentitan.org>

Signed-off-by: Michael Schaffner <msf@opentitan.org>

Some core files were missing, and there were also some syntax errors.

Signed-off-by: Alexander Williams <awill@opentitan.org>

Add 1r1w RAM configuration as an option for spi_device for tech nodes
where the 2p RAM configuration is not available. Make the 2p RAM have
the same access controls as the 1r1w RAM, so the two behave the same
way.

Also add word initialization circuitry on the SPI side, to init parity.
The SPI -> core buffer for the payload uses parity and SW has no way of
initializing it since the the write port is in the SPI domain. Since the SPI
side writes the payload byte by byte, we need to guard against partially
initialized 32bit wordd, because these could cause TL-UL bus errors upon
readout. Unfortunately, an initialization circuit that initializes the entire
SRAM on the SPI clock domain is infeasible since that clock is only
intermittently available. Hence, we keep track of uninitialized words using a
valid bit array, and upon the first write to a word, uninitialized bytes are
set to zero if the write operation is a sub-word write op.

Note that in this commit, DV tests have focused much more on the 2p
variant.

Signed-off-by: Alexander Williams <awill@opentitan.org>
Co-authored-by: Michael Schaffner <msf@opentitan.org>

Add params for the DPRAM offsets so they are available in C headers for
software.

Signed-off-by: Alexander Williams <awill@opentitan.org>