[spi_device] Add support for 1r1w RAMs and parity init #20942
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Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
Signed-off-by: Michael Schaffner <msf@opentitan.org>
Signed-off-by: Michael Schaffner <msf@opentitan.org>
Signed-off-by: Michael Schaffner <msf@opentitan.org>
Some core files were missing, and there were also some syntax errors. Signed-off-by: Alexander Williams <awill@opentitan.org>
a-will
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Component:DV
a-will
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hw/ip/spi_device/rtl/spid_dpram.sv
Outdated
| spi2sys_rd_req, | ||
| spi2sys_rd_addr | ||
| }; | ||
| end else if (SramType == SramType1r1w) begin : ram1r1w |
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nitnit: we should fix up these block labels as the linter says
msfschaffner
approved these changes
Jan 23, 2024
Yes, I squashed that all down, since it was noise. |
Add 1r1w RAM configuration as an option for spi_device for tech nodes where the 2p RAM configuration is not available. Make the 2p RAM have the same access controls as the 1r1w RAM, so the two behave the same way. Also add word initialization circuitry on the SPI side, to init parity. The SPI -> core buffer for the payload uses parity and SW has no way of initializing it since the the write port is in the SPI domain. Since the SPI side writes the payload byte by byte, we need to guard against partially initialized 32bit wordd, because these could cause TL-UL bus errors upon readout. Unfortunately, an initialization circuit that initializes the entire SRAM on the SPI clock domain is infeasible since that clock is only intermittently available. Hence, we keep track of uninitialized words using a valid bit array, and upon the first write to a word, uninitialized bytes are set to zero if the write operation is a sub-word write op. Note that in this commit, DV tests have focused much more on the 2p variant. Signed-off-by: Alexander Williams <awill@opentitan.org> Co-authored-by: Michael Schaffner <msf@opentitan.org>
Add params for the DPRAM offsets so they are available in C headers for software. Signed-off-by: Alexander Williams <awill@opentitan.org>
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Add 1r1w RAM configuration as an option for spi_device for tech nodes where the 2p RAM configuration is not available. Make the 2p RAM have the same access controls as the 1r1w RAM, so the two behave the same way.
Also add word initialization circuitry on the SPI side, to init parity. The SPI -> core buffer for the payload uses parity and SW has no way of initializing it since the the write port is in the SPI domain. Since the SPI side writes the payload byte by byte, we need to guard against partially initialized 32bit wordd, because these could cause TL-UL bus errors upon readout. Unfortunately, an initialization circuit that initializes the entire SRAM on the SPI clock domain is infeasible since that clock is only intermittently available. Hence, we keep track of uninitialized words using a valid bit array, and upon the first write to a word, uninitialized bytes are set to zero if the write operation is a sub-word write op.
Note that in this PR, DV tests have focused much more on the 2p variant, though.
This is largely a set of cherry-picks from integrated_dev, after resolving conflicts. However, the last commit adds fixed "parameters" for DPRAM offsets and makes them available as macros to C.
Resolves #5369