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  • ShanghaiTech University
  • Pudong, Shanghai

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luojw-dwr/README.md

User Profile

This is Jianwen Luo from ShanghaiTech University.

  • I'm currently working on both using and designing HLS (High-Level Synthesis).
  • I used to design on FPGA in Verilog and Chisel3.
  • I'm interested in fancy stuffs like mathematics ...
  • and type systems and programming languages.

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  1. ABG ABG Public

    Python