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  • AMD
  • Cambridge, United Kingdom

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  1. MSHR-rich MSHR-rich Public

    A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory acc…

    VHDL 18 6

  2. dynaburst dynaburst Public

    An evolution of our multi-banked nonblocking cache that uses bursts to extract additional bandwidth from DRAM when access patterns are short and irregular.

    VHDL 6 2

  3. ntds-2019-team-49-fpga ntds-2019-team-49-fpga Public

    Understanding Negotiated-Congestion Routing for FPGAs

    Jupyter Notebook 3 1