core: add ElasticBuffer to replace AsyncFIFO

TODO

@@ -1,4 +1,3 @@
-- use elastic buffers between transport layer and links.
 - use GTX's QPLL for linerate > 6.6Gbps.
 - (later) add deterministic latency.
 - (optional) test PRBS generators and use them (we are currently using PRBS generators from the transceivers).

jesd204b/core.py

@@ -3,7 +3,6 @@
 
 from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.interconnect.csr import *
@@ -13,6 +12,36 @@
 from jesd204b.link import JESD204BLinkTX
 
 
+class ElasticBuffer(Module):
+    def __init__(self, data_width, depth, initial_delay=0):
+        self.din = Signal(data_width)
+        self.dout = Signal(data_width)
+
+        # # #
+
+        wrpointer = Signal(max=depth, reset=initial_delay)
+        rdpointer = Signal(max=depth)
+
+        storage = Memory(data_width, depth)
+        self.specials += storage
+
+        wrport = storage.get_port(write_capable=True, clock_domain="write")
+        rdport = storage.get_port(clock_domain="read")
+        self.specials += wrport, rdport
+
+        self.sync.write += wrpointer.eq(wrpointer + 1)
+        self.sync.read += rdpointer.eq(rdpointer + 1)
+
+        self.comb += [
+            wrport.we.eq(1),
+            wrport.adr.eq(wrpointer),
+            wrport.dat_w.eq(self.din),
+
+            rdport.adr.eq(rdpointer),
+            self.dout.eq(rdport.dat_r)
+        ]
+
+
 class JESD204BCoreTX(Module):
     def __init__(self, phys, jesd_settings, converter_data_width):
         self.enable = Signal()
@@ -32,12 +61,14 @@ def __init__(self, phys, jesd_settings, converter_data_width):
         # clocking
         # phys
         for n, phy in enumerate(phys):
-            cd_phy = ClockDomain("phy"+str(n))
+            self.clock_domains.cd_phy = ClockDomain("phy"+str(n))
             self.comb += [
-                cd_phy.clk.eq(phy.gtx.cd_tx.clk),
-                cd_phy.rst.eq(phy.gtx.cd_tx.rst)
+                self.cd_phy.clk.eq(phy.gtx.cd_tx.clk),
+                self.cd_phy.rst.eq(phy.gtx.cd_tx.rst)
             ]
-            self.clock_domains += cd_phy
+            self.clock_domains.cd_ebuf = ClockDomain("ebuf"+str(n))
+            self.comb += self.cd_ebuf.clk.eq(self.cd_phy.clk)
+            self.specials += AsyncResetSynchronizer(self.cd_ebuf, ~ready)
         # user
         self.clock_domains.cd_user = ClockDomain()
         self.comb += self.cd_user.clk.eq(ClockSignal("phy0"))
@@ -67,9 +98,9 @@ def __init__(self, phys, jesd_settings, converter_data_width):
         # buffers
         self.bufs = bufs = []
         for n, phy in enumerate(phys):
-            buf = AsyncFIFO(len(phy.data), 8) # FIXME use elastic buffers
+            buf = ElasticBuffer(len(phy.data), 8, 4)
             buf = ClockDomainsRenamer(
-                {"write": "user", "read": "phy"+str(n)})(buf)
+                {"write": "user", "read": "ebuf"+str(n)})(buf)
             bufs.append(buf)
             self.submodules += buf
 
@@ -86,9 +117,7 @@ def __init__(self, phys, jesd_settings, converter_data_width):
         # connect modules together
         for n, (link, buf) in enumerate(zip(links, bufs)):
             self.comb += [
-                buf.we.eq(1),
                 buf.din.eq(getattr(transport.source, "lane"+str(n))),
-                buf.re.eq(1),
                 link.sink.data.eq(buf.dout),
                 phys[n].data.eq(link.source.data),
                 phys[n].ctrl.eq(link.source.ctrl)