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Original file line number | Diff line number | Diff line change |
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@@ -1,4 +1,3 @@ | ||
- use elastic buffers between transport layer and links. | ||
- use GTX's QPLL for linerate > 6.6Gbps. | ||
- (later) add deterministic latency. | ||
- (optional) test PRBS generators and use them (we are currently using PRBS generators from the transceivers). |
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@@ -3,7 +3,6 @@ | |
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from migen import * | ||
from migen.genlib.cdc import MultiReg | ||
from migen.genlib.fifo import AsyncFIFO | ||
from migen.genlib.resetsync import AsyncResetSynchronizer | ||
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from misoc.interconnect.csr import * | ||
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@@ -13,6 +12,36 @@ | |
from jesd204b.link import JESD204BLinkTX | ||
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class ElasticBuffer(Module): | ||
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def __init__(self, data_width, depth, initial_delay=0): | ||
self.din = Signal(data_width) | ||
self.dout = Signal(data_width) | ||
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# # # | ||
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wrpointer = Signal(max=depth, reset=initial_delay) | ||
rdpointer = Signal(max=depth) | ||
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storage = Memory(data_width, depth) | ||
self.specials += storage | ||
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wrport = storage.get_port(write_capable=True, clock_domain="write") | ||
rdport = storage.get_port(clock_domain="read") | ||
self.specials += wrport, rdport | ||
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self.sync.write += wrpointer.eq(wrpointer + 1) | ||
self.sync.read += rdpointer.eq(rdpointer + 1) | ||
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jordens
Member
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self.comb += [ | ||
wrport.we.eq(1), | ||
wrport.adr.eq(wrpointer), | ||
wrport.dat_w.eq(self.din), | ||
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rdport.adr.eq(rdpointer), | ||
self.dout.eq(rdport.dat_r) | ||
] | ||
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class JESD204BCoreTX(Module): | ||
def __init__(self, phys, jesd_settings, converter_data_width): | ||
self.enable = Signal() | ||
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@@ -32,12 +61,14 @@ def __init__(self, phys, jesd_settings, converter_data_width): | |
# clocking | ||
# phys | ||
for n, phy in enumerate(phys): | ||
cd_phy = ClockDomain("phy"+str(n)) | ||
self.clock_domains.cd_phy = ClockDomain("phy"+str(n)) | ||
self.comb += [ | ||
cd_phy.clk.eq(phy.gtx.cd_tx.clk), | ||
cd_phy.rst.eq(phy.gtx.cd_tx.rst) | ||
self.cd_phy.clk.eq(phy.gtx.cd_tx.clk), | ||
self.cd_phy.rst.eq(phy.gtx.cd_tx.rst) | ||
] | ||
self.clock_domains += cd_phy | ||
self.clock_domains.cd_ebuf = ClockDomain("ebuf"+str(n)) | ||
self.comb += self.cd_ebuf.clk.eq(self.cd_phy.clk) | ||
self.specials += AsyncResetSynchronizer(self.cd_ebuf, ~ready) | ||
# user | ||
self.clock_domains.cd_user = ClockDomain() | ||
self.comb += self.cd_user.clk.eq(ClockSignal("phy0")) | ||
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@@ -67,9 +98,9 @@ def __init__(self, phys, jesd_settings, converter_data_width): | |
# buffers | ||
self.bufs = bufs = [] | ||
for n, phy in enumerate(phys): | ||
buf = AsyncFIFO(len(phy.data), 8) # FIXME use elastic buffers | ||
buf = ElasticBuffer(len(phy.data), 8, 4) | ||
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buf = ClockDomainsRenamer( | ||
{"write": "user", "read": "phy"+str(n)})(buf) | ||
{"write": "user", "read": "ebuf"+str(n)})(buf) | ||
bufs.append(buf) | ||
self.submodules += buf | ||
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@@ -86,9 +117,7 @@ def __init__(self, phys, jesd_settings, converter_data_width): | |
# connect modules together | ||
for n, (link, buf) in enumerate(zip(links, bufs)): | ||
self.comb += [ | ||
buf.we.eq(1), | ||
buf.din.eq(getattr(transport.source, "lane"+str(n))), | ||
buf.re.eq(1), | ||
link.sink.data.eq(buf.dout), | ||
phys[n].data.eq(link.source.data), | ||
phys[n].ctrl.eq(link.source.ctrl) | ||
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This should move to misoc.