better clocking: remove cd_name parameters from gtx, redefine clock d…

…omains in core

jesd204b/core.py

@@ -29,15 +29,24 @@ def __init__(self, phys, jesd_settings, converter_data_width):
 
         ready = Signal()
 
-        # clocking (use clock from first phy for core clock)
-        self.clock_domains.cd_tx = ClockDomain("jesd_tx_core")
-        self.comb += self.cd_tx.clk.eq(phys[0].gtx.cd_tx.clk)
-        self.specials += AsyncResetSynchronizer(self.cd_tx, ~ready)
+        # clocking
+        # phys
+        for n, phy in enumerate(phys):
+            cd_phy = ClockDomain("phy"+str(n))
+            self.comb += [
+                cd_phy.clk.eq(phy.gtx.cd_tx.clk),
+                cd_phy.rst.eq(phy.gtx.cd_tx.rst)
+            ]
+            self.clock_domains += cd_phy
+        # user
+        self.clock_domains.cd_user = ClockDomain()
+        self.comb += self.cd_user.clk.eq(ClockSignal("phy0"))
+        self.specials += AsyncResetSynchronizer(self.cd_user, ~ready)
 
         # transport layer
         transport = JESD204BTransportTX(jesd_settings,
                                             converter_data_width)
-        transport = ClockDomainsRenamer("jesd_tx_core")(transport)
+        transport = ClockDomainsRenamer("user")(transport)
         self.submodules.transport = transport
 
         # stpl
@@ -47,7 +56,7 @@ def __init__(self, phys, jesd_settings, converter_data_width):
         self.submodules += stpl
         self.specials += MultiReg(self.stpl_enable,
                                   stpl_enable,
-                                  "jesd_tx_core")
+                                  "user")
         self.comb += \
             If(stpl_enable,
                 transport.sink.eq(stpl.source)
@@ -57,18 +66,18 @@ def __init__(self, phys, jesd_settings, converter_data_width):
 
         # buffers
         self.bufs = bufs = []
-        for phy in phys:
+        for n, phy in enumerate(phys):
             buf = AsyncFIFO(len(phy.data), 8) # FIXME use elastic buffers
             buf = ClockDomainsRenamer(
-                {"write": "jesd_tx_core", "read": phy.gtx.cd_tx.name})(buf)
+                {"write": "user", "read": "phy"+str(n)})(buf)
             bufs.append(buf)
             self.submodules += buf
 
         # link layer
         self.links = links = []
         for n, phy in enumerate(phys):
             link = JESD204BLinkTX(len(phy.data), jesd_settings, n)
-            link = ClockDomainsRenamer(phy.gtx.cd_tx.name)(link)
+            link = ClockDomainsRenamer("phy"+str(n))(link)
             links.append(link)
             self.comb += link.start.eq(self.start)
             self.submodules += link
@@ -86,12 +95,12 @@ def __init__(self, phys, jesd_settings, converter_data_width):
             ]
 
         # control
-        for phy in phys:
+        for n, phy in enumerate(phys):
             self.comb += phy.gtx.gtx_init.restart.eq(~self.enable)
             self.specials += MultiReg(self.prbs_config,
                                       phy.gtx.prbs_config,
-                                      phy.gtx.cd_tx.name)
-        self.specials +=  MultiReg(~self.cd_tx.rst, self.ready)
+                                      "phy"+str(n))
+        self.specials +=  MultiReg(~self.cd_user.rst, self.ready)
 
 
 class JESD204BCoreTXControl(Module, AutoCSR):

jesd204b/phy/__init__.py

@@ -5,7 +5,7 @@
 
 
 class JESD204BPhyTX(Module):
-    def __init__(self, pll, tx_pads, sys_clk_freq, n=0):
+    def __init__(self, pll, tx_pads, sys_clk_freq):
         self.data = Signal(32)
         self.ctrl = Signal(32//8)
 
@@ -15,8 +15,7 @@ def __init__(self, pll, tx_pads, sys_clk_freq, n=0):
         self.submodules.gtx = GTXTransmitter(
                 pll=pll,
                 tx_pads=tx_pads,
-                sys_clk_freq=sys_clk_freq,
-                cd_name="jesd_tx_phy"+str(n))
+                sys_clk_freq=sys_clk_freq)
 
         for i in range(32//8):
             self.comb += [

jesd204b/phy/gtx.py

@@ -125,7 +125,7 @@ def compute_config(cls, refclk_freq, linerate):
 
 
 class GTXTransmitter(Module):
-    def __init__(self, pll, tx_pads, sys_clk_freq, cd_name):
+    def __init__(self, pll, tx_pads, sys_clk_freq):
         self.prbs_config = Signal(4)
         self.produce_square_wave = Signal()
 
@@ -204,8 +204,8 @@ def __init__(self, pll, tx_pads, sys_clk_freq, cd_name):
                 i_TXCHARDISPMODE=Cat(*[txdata[10*i+9] for i in range(nwords)]),
                 i_TXCHARDISPVAL=Cat(*[txdata[10*i+8] for i in range(nwords)]),
                 i_TXDATA=Cat(*[txdata[10*i:10*i+8] for i in range(nwords)]),
-                i_TXUSRCLK=ClockSignal(cd_name),
-                i_TXUSRCLK2=ClockSignal(cd_name),
+                i_TXUSRCLK=ClockSignal("tx"),
+                i_TXUSRCLK2=ClockSignal("tx"),
 
                 # TX electrical
                 i_TXBUFDIFFCTRL=0b100,
@@ -216,13 +216,13 @@ def __init__(self, pll, tx_pads, sys_clk_freq, cd_name):
                 o_GTXTXN=tx_pads.txn
             )
 
-        self.clock_domains.cd_tx = ClockDomain(cd_name)
+        self.clock_domains.cd_tx = ClockDomain()
         self.specials += Instance("BUFG",
             i_I=txoutclk, o_O=self.cd_tx.clk)
         self.specials += AsyncResetSynchronizer(
             self.cd_tx, ~self.gtx_init.done)
 
-        self.submodules.encoder = ClockDomainsRenamer(cd_name)(Encoder(nwords, True))
+        self.submodules.encoder = ClockDomainsRenamer("tx")(Encoder(nwords, True))
         self.comb += \
             If(self.produce_square_wave,
                 # square wave @ linerate/40 for scope observation