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How to link between Migen and Icarus Iverilog For simulation?? #122
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The docs you are reading are out of date, there is the migen built-in simulator now that does not require an external simulator. If you do want to use Icarus, you can resurrect the old migen code. |
from migen import *
from migen.sim.vcd import VCDWriter, DummyVCDWriter
class ORGate(Module):
def __init__(self):
self.a = Signal()
self.b = Signal()
self.x = Signal()
###
self.comb += self.x.eq(self.a | self.b)
dut = ORGate()
def testbench():
yield dut.a.eq(0)
yield dut.b.eq(0)
yield
assert (yield dut.x) == 0
yield dut.a.eq(0)
yield dut.b.eq(1)
yield
assert (yield dut.x) == 1
run_simulation(dut, testbench(),vcd_name="file.vcd")
i Ran this code ,But i am not getting any output,its just executing
…On Tue, Jul 31, 2018 at 5:46 PM, Sébastien Bourdeauducq < ***@***.***> wrote:
The docs you are reading are out of date, there is the migen built-in
simulator now that does not require an external simulator. If you do want
to use Icarus, you can resurrect the old migen code.
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<#122 (comment)>, or mute
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|
sorry Got it...
…On Tue, Jul 31, 2018 at 5:46 PM, Sébastien Bourdeauducq < ***@***.***> wrote:
The docs you are reading are out of date, there is the migen built-in
simulator now that does not require an external simulator. If you do want
to use Icarus, you can resurrect the old migen code.
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub
<#122 (comment)>, or mute
the thread
<https://github.com/notifications/unsubscribe-auth/AWjrOTZBxxUnTijb765BaXiPtOaRFofmks5uMEqxgaJpZM4VoIos>
.
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As given in docs i am not able to understand how to link to iverilog and simulate it further in gtkwave.
I am not able to understand "make" commands in docs
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