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Added sm7125.dtsi and a72q dts
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Added a72q postmarketos config
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@map220v
map220v committed Oct 3, 2022
1 parent 4fe89d0 commit e436882
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1 change: 1 addition & 0 deletions arch/arm64/boot/dts/qcom/Makefile
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Expand Up @@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-samsung-a72q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
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277 changes: 277 additions & 0 deletions arch/arm64/boot/dts/qcom/sm7125-samsung-a72q.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* SM7125 Samsung Galaxy A72 (a72q) specific device tree
*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sm7125.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"

/delete-node/ &rmtfs_mem;
/delete-node/ &ipa_fw_mem;

/ {
model = "Samsung Galaxy A72";
compatible = "samsung,a72q", "qcom,sm7125";
qcom,msm-id = <443 0x0>;
qcom,board-id = <0x22 0x5>;

reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

framebuffer_region@9c000000 {
reg = <0x0 0x9c000000 0x0 0x01800000>;
no-map;
};

mpss_mem: memory@86000000 {
reg = <0x0 0x8b000000 0x0 0x8900000>;
no-map;
};

venus_mem: memory@8ee00000 {
reg = <0 0x98400000 0 0x500000>;
no-map;
};

wlan_mem: memory@93900000 {
reg = <0x0 0x93900000 0x0 0x200000>;
no-map;
};

ipa_fw_mem: memory@93b00000 {
reg = <0x0 0x93b00000 0x0 0x10000>;
no-map;
};

ramoops@B4600000 {
compatible = "ramoops";
reg = <0x0 0xb4600000 0x0 0x100000>;
record-size = <0x40000>;
console-size = <0x40000>;
ftrace-size = <0x40000>;
pmsg-size = <0x40000>;
};

rmtfs_mem: memory@f3701000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xf3701000 0 0x200000>;
no-map;

qcom,client-id = <1>;
//qcom,vmid = <15>;
};
};

chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer@9c000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>;
width = <1080>;
height = <2400>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
/*
* That's a lot of clocks, but it's necessary due
* to unused clk cleanup & no panel driver yet..
*/
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
power-domains = <&dispcc MDSS_GDSC>;
};
};
};

&apps_rsc {
pm6150-rpmh-regulators {
compatible = "qcom,pm6150-rpmh-regulators";
qcom,pmic-id = "a";

vreg_l4a: ldo4 {
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <928000>;
};

vreg_l11a: ldo11 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1904000>;
};

vreg_l12a: ldo12 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1950000>;
};

vreg_l17a: ldo17 {
regulator-min-microvolt = <2920000>;
regulator-max-microvolt = <3232000>;
};

vreg_l19a: ldo19 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <2960000>;
};
};

pm6150l-rpmh-regulators {
compatible = "qcom,pm6150l-rpmh-regulators";
qcom,pmic-id = "c";

vreg_l3c: ldo3 {
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1304000>;
};

vreg_l6c: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};

vreg_l9c: ldo9 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
};
};
};

&tlmm {
gpio-reserved-ranges = <59 4>;

sdc2_on: sdc2-on {
pinconf-clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};

pinconf-cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};

pinconf-data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};

pinconf-sd-cd {
pins = "gpio69";
bias-pull-up;
drive-strength = <2>;
};
};

sdc2_off: sdc2-off {
pinconf-clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};

pinconf-cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};

pinconf-data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};

pinconf-sd-cd {
pins = "gpio69";
bias-pull-up;
drive-strength = <2>;
};
};
};

&ipa {
status = "okay";

memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sm7125/a72q/ipa_fws.mdt";
};

&sdhc_2 {
status = "okay";

pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
vmmc-supply = <&vreg_l9c>;
vqmmc-supply = <&vreg_l6c>;

cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
};

&ufs_mem_hc {
status = "okay";

vcc-supply = <&vreg_l19a>;
vcc-max-microamp = <600000>;
vccq2-supply = <&vreg_l12a>;
vccq2-max-microamp = <600000>;
};

&ufs_mem_phy {
status = "okay";

vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l3c>;
vdda-phy-max-microamp = <62900>;
vdda-pll-max-microamp = <18300>;
};

&usb_1 {
status = "okay";
};

&usb_1_dwc3 {
dr_mode = "peripheral";
};

&usb_1_hsphy {
status = "okay";
vdd-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l11a>;
vdda-phy-dpdm-supply = <&vreg_l17a>;
};

&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l3c>;
};

&lpasscc {
status = "disabled";
};

&lpass_cpu {
status = "disabled";
};

&lpass_hm {
status = "disabled";
};
94 changes: 94 additions & 0 deletions arch/arm64/boot/dts/qcom/sm7125.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Snapdragon 720G (sm7125) specific device tree
*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/

#include "sc7180.dtsi"

/* SM7125 uses Kryo 465 instead of Kryo 468 */
&CPU0 { compatible = "qcom,kryo465"; };
&CPU1 { compatible = "qcom,kryo465"; };
&CPU2 { compatible = "qcom,kryo465"; };
&CPU3 { compatible = "qcom,kryo465"; };
&CPU4 { compatible = "qcom,kryo465"; };
&CPU5 { compatible = "qcom,kryo465"; };
&CPU6 { compatible = "qcom,kryo465"; };
&CPU7 { compatible = "qcom,kryo465"; };

// SC7180 doesn't have UFS yet.
&soc {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm7125-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>,
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
power-domains = <&gcc UFS_PHY_GDSC>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";

iommus = <&apps_smmu 0xa0 0x0>;

clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"ice_core_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>;

status = "disabled";
};

ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm7125-qmp-ufs-phy";
reg = <0 0x01d87000 0 0xddc>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";

ufs_mem_phy_lanes: lanes@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
};
};
};
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