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1. tt06_maxluppe_alfsr tt06_maxluppe_alfsr Public

   This project implements a LFSR with configurable delay lines, instead of Registers, to act as a chaotic oscilator

   Verilog 2

2. tt07_maxluppe_Digital_DAC_Comp tt07_maxluppe_Digital_DAC_Comp Public

   All digital analog circuits

   Verilog 1

3. Mixed-signal-RISCV-based-SoC-on-FPGA Mixed-signal-RISCV-based-SoC-on-FPGA Public

   From 2-input mux to RISC-V to FPGA OSFPGA Foundation promotion

4. tt07_maxluppe_NIST tt07_maxluppe_NIST Public

   Implementation of NIST's Frequency Monobit and Frequency Block Tests

   Verilog

5. tt08_maxluppe_uP_SEL0628_2024 tt08_maxluppe_uP_SEL0628_2024 Public

   Microprocessor developed by students of the discipline SEL0628-Digital Systems of the Computer Engineering course at USP - São Carlos campus

   Verilog

6. tt08_maxluppe_mcpu tt08_maxluppe_mcpu Public

   Tim Böscke's Minimal 8Bit CPU in a 32 Macrocell CPLD

   Verilog