Skip to content

Commit 7b2c4cd

Browse files
pm215pm215
committed
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210210' into staging
ppc patch queue for 20201-02-10 Here's the latest batch of patches for the ppc target and machine types. Highlights are: * Several fixes for E500 from Bin Meng * Fixes and cleanups for PowerNV from Cédric Le Goater * Assorted other fixes and cleanups # gpg: Signature made Wed 10 Feb 2021 06:16:53 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.0-20210210: target/ppc: Add E500 L2CSR0 write helper hw/net: fsl_etsec: Reverse the RCTRL.RSF logic hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes hw/ppc: e500: Use a macro for the platform clock frequency ppc/pnv: Set default RAM size to 1 GB spapr_numa.c: fix ibm,max-associativity-domains calculation spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helper spapr: move spapr_machine_using_legacy_numa() to spapr_numa.c ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR ppc/pnv: Remove default disablement of the PNOR contents ppc/pnv: Discard internal BMC initialization when BMC is external ppc/pnv: Simplify pnv_bmc_create() ppc/pnv: Use skiboot addresses to load kernel and ramfs ppc/xive: Add firmware bit when dumping the ENDs ppc/pnv: Add trace events for PCI event notification target/ppc: Remove unused MMU definitions spapr: Adjust firmware path of PCI devices spapr.c: add 'name' property for hotplugged CPUs nodes spapr.c: use g_auto* with 'nodename' in CPU DT functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 parents 1214d55 + 298091f commit 7b2c4cd

File tree

20 files changed

+150
-77
lines changed

20 files changed

+150
-77
lines changed

‎hw/intc/pnv_xive.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424
#include "hw/ppc/xive_regs.h"
2525
#include "hw/qdev-properties.h"
2626
#include "hw/ppc/ppc.h"
27+
#include "trace.h"
2728

2829
#include <libfdt.h>
2930

@@ -1319,6 +1320,8 @@ static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val)
13191320
uint8_t blk;
13201321
uint32_t idx;
13211322

1323+
trace_pnv_xive_ic_hw_trigger(addr, val);
1324+
13221325
if (val & XIVE_TRIGGER_END) {
13231326
xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64,
13241327
addr, val);

‎hw/intc/trace-events‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -236,3 +236,6 @@ xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x0x%"P
236236
xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x0x%"PRIx64" sz=%d val=0x%" PRIx64
237237
xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x"
238238
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x0x%"PRIx64
239+
240+
# pnv_xive.c
241+
pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=0x%"PRIx64

‎hw/intc/xive.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1294,7 +1294,7 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon)
12941294

12951295
pq = xive_get_field32(END_W1_ESn, end->w1);
12961296

1297-
monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
1297+
monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
12981298
end_idx,
12991299
pq & XIVE_ESB_VAL_P ? 'P' : '-',
13001300
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
@@ -1305,6 +1305,7 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon)
13051305
xive_end_is_escalate(end) ? 'e' : '-',
13061306
xive_end_is_uncond_escalation(end) ? 'u' : '-',
13071307
xive_end_is_silent_escalation(end) ? 's' : '-',
1308+
xive_end_is_firmware(end) ? 'f' : '-',
13081309
priority, nvt_blk, nvt_idx);
13091310

13101311
if (qaddr_base) {

‎hw/net/fsl_etsec/rings.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -502,7 +502,7 @@ ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size)
502502
return -1;
503503
}
504504

505-
if ((etsec->regs[RCTRL].value & RCTRL_RSF) && (size < 60)) {
505+
if (!(etsec->regs[RCTRL].value & RCTRL_RSF) && (size < 60)) {
506506
/* CRC is not in the packet yet, so short frame is below 60 bytes */
507507
RING_DEBUG("%s: Drop short frame\n", __func__);
508508
return -1;

‎hw/pci-host/pnv_phb4.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include "hw/irq.h"
2323
#include "hw/qdev-properties.h"
2424
#include "qom/object.h"
25+
#include "trace.h"
2526

2627
#define phb_error(phb, fmt, ...) \
2728
qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \
@@ -1257,6 +1258,8 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno)
12571258
uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
12581259
MemTxResult result;
12591260

1261+
trace_pnv_phb4_xive_notify(notif_port, data);
1262+
12601263
address_space_stq_be(&address_space_memory, notif_port, data,
12611264
MEMTXATTRS_UNSPECIFIED, &result);
12621265
if (result != MEMTX_OK) {

‎hw/pci-host/trace-events‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,3 +20,6 @@ unin_data_write(uint64_t addr, unsigned len, uint64_t val) "write addr 0x%"PRIx6
2020
unin_data_read(uint64_t addr, unsigned len, uint64_t val) "read addr 0x%"PRIx64 " len %d val 0x%"PRIx64
2121
unin_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
2222
unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
23+
24+
# pnv_phb4.c
25+
pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64" data=0x%"PRIx64

‎hw/ppc/e500.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,8 @@
7474
#define MPC8544_I2C_IRQ 43
7575
#define RTC_REGS_OFFSET 0x68
7676

77+
#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
78+
7779
struct boot_info
7880
{
7981
uint32_t dt_base;
@@ -124,7 +126,7 @@ static void dt_serial_create(void *fdt, unsigned long long offset,
124126
qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
125127
qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
126128
qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
127-
qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
129+
qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
128130
qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
129131
qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
130132
qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
@@ -320,8 +322,8 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
320322
int fdt_size;
321323
void *fdt;
322324
uint8_t hypercall[16];
323-
uint32_t clock_freq = 400000000;
324-
uint32_t tb_freq = 400000000;
325+
uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
326+
uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
325327
int i;
326328
char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
327329
char *soc;
@@ -890,7 +892,7 @@ void ppce500_init(MachineState *machine)
890892
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
891893
env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
892894

893-
ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
895+
ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
894896

895897
/* Register reset handler */
896898
if (!i) {

‎hw/ppc/pnv.c‎

Lines changed: 21 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "qemu-common.h"
2222
#include "qemu/datadir.h"
2323
#include "qemu/units.h"
24+
#include "qemu/cutils.h"
2425
#include "qapi/error.h"
2526
#include "sysemu/qtest.h"
2627
#include "sysemu/sysemu.h"
@@ -65,9 +66,9 @@
6566
#define FW_MAX_SIZE (16 * MiB)
6667

6768
#define KERNEL_LOAD_ADDR 0x20000000
68-
#define KERNEL_MAX_SIZE (256 * MiB)
69-
#define INITRD_LOAD_ADDR 0x60000000
70-
#define INITRD_MAX_SIZE (256 * MiB)
69+
#define KERNEL_MAX_SIZE (128 * MiB)
70+
#define INITRD_LOAD_ADDR 0x28000000
71+
#define INITRD_MAX_SIZE (128 * MiB)
7172

7273
static const char *pnv_chip_core_typename(const PnvChip *o)
7374
{
@@ -725,8 +726,11 @@ static void pnv_init(MachineState *machine)
725726
DeviceState *dev;
726727

727728
/* allocate RAM */
728-
if (machine->ram_size < (1 * GiB)) {
729-
warn_report("skiboot may not work with < 1GB of RAM");
729+
if (machine->ram_size < mc->default_ram_size) {
730+
char *sz = size_to_str(mc->default_ram_size);
731+
error_report("Invalid RAM size, should be bigger than %s", sz);
732+
g_free(sz);
733+
exit(EXIT_FAILURE);
730734
}
731735
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
732736

@@ -871,6 +875,14 @@ static void pnv_init(MachineState *machine)
871875
pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
872876
}
873877

878+
/*
879+
* The PNOR is mapped on the LPC FW address space by the BMC.
880+
* Since we can not reach the remote BMC machine with LPC memops,
881+
* map it always for now.
882+
*/
883+
memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
884+
&pnv->pnor->mmio);
885+
874886
/*
875887
* OpenPOWER systems use a IPMI SEL Event message to notify the
876888
* host to powerdown
@@ -1150,6 +1162,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
11501162
qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
11511163
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
11521164

1165+
chip->fw_mr = &chip8->lpc.isa_fw;
11531166
chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
11541167
(uint64_t) PNV_XSCOM_BASE(chip),
11551168
PNV_XSCOM_LPC_BASE);
@@ -1479,6 +1492,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
14791492
memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
14801493
&chip9->lpc.xscom_regs);
14811494

1495+
chip->fw_mr = &chip9->lpc.isa_fw;
14821496
chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
14831497
(uint64_t) PNV9_LPCM_BASE(chip));
14841498

@@ -1592,6 +1606,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
15921606
memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
15931607
&chip10->lpc.xscom_regs);
15941608

1609+
chip->fw_mr = &chip10->lpc.isa_fw;
15951610
chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
15961611
(uint64_t) PNV10_LPCM_BASE(chip));
15971612
}
@@ -1983,7 +1998,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
19831998
* RAM defaults to less than 2048 for 32-bit hosts, and large
19841999
* enough to fit the maximum initrd size at it's load address
19852000
*/
1986-
mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
2001+
mc->default_ram_size = 1 * GiB;
19872002
mc->default_ram_id = "pnv.ram";
19882003
ispc->print_info = pnv_pic_print_info;
19892004
nc->nmi_monitor_handler = pnv_nmi;

‎hw/ppc/pnv_bmc.c‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,11 @@ typedef struct OemSel {
5151
#define SOFT_OFF 0x00
5252
#define SOFT_REBOOT 0x01
5353

54+
static bool pnv_bmc_is_simulator(IPMIBmc *bmc)
55+
{
56+
return object_dynamic_cast(OBJECT(bmc), TYPE_IPMI_BMC_SIMULATOR);
57+
}
58+
5459
static void pnv_gen_oem_sel(IPMIBmc *bmc, uint8_t reboot)
5560
{
5661
/* IPMI SEL Event are 16 bytes long */
@@ -79,6 +84,10 @@ void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt)
7984
const struct ipmi_sdr_compact *sdr;
8085
uint16_t nextrec;
8186

87+
if (!pnv_bmc_is_simulator(bmc)) {
88+
return;
89+
}
90+
8291
offset = fdt_add_subnode(fdt, 0, "bmc");
8392
_FDT(offset);
8493

@@ -243,6 +252,10 @@ static const IPMINetfn hiomap_netfn = {
243252

244253
void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor)
245254
{
255+
if (!pnv_bmc_is_simulator(bmc)) {
256+
return;
257+
}
258+
246259
object_ref(OBJECT(pnor));
247260
object_property_add_const_link(OBJECT(bmc), "pnor", OBJECT(pnor));
248261

@@ -260,13 +273,8 @@ IPMIBmc *pnv_bmc_create(PnvPnor *pnor)
260273
Object *obj;
261274

262275
obj = object_new(TYPE_IPMI_BMC_SIMULATOR);
263-
object_ref(OBJECT(pnor));
264-
object_property_add_const_link(obj, "pnor", OBJECT(pnor));
265276
qdev_realize(DEVICE(obj), NULL, &error_fatal);
266-
267-
/* Install the HIOMAP protocol handlers to access the PNOR */
268-
ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(obj), IPMI_NETFN_OEM,
269-
&hiomap_netfn);
277+
pnv_bmc_set_pnor(IPMI_BMC(obj), pnor);
270278

271279
return IPMI_BMC(obj);
272280
}
@@ -291,7 +299,7 @@ static int bmc_find(Object *child, void *opaque)
291299

292300
IPMIBmc *pnv_bmc_find(Error **errp)
293301
{
294-
ForeachArgs args = { TYPE_IPMI_BMC_SIMULATOR, NULL };
302+
ForeachArgs args = { TYPE_IPMI_BMC, NULL };
295303
int ret;
296304

297305
ret = object_child_foreach_recursive(object_get_root(), bmc_find, &args);

‎hw/ppc/pnv_lpc.c‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -824,8 +824,6 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
824824
ISABus *isa_bus;
825825
qemu_irq *irqs;
826826
qemu_irq_handler handler;
827-
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
828-
bool hostboot_mode = !!pnv->fw_load_addr;
829827

830828
/* let isa_bus_new() create its own bridge on SysBus otherwise
831829
* devices specified on the command line won't find the bus and
@@ -851,18 +849,5 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
851849

852850
isa_bus_irqs(isa_bus, irqs);
853851

854-
/*
855-
* TODO: Map PNOR on the LPC FW address space on demand ?
856-
*/
857-
memory_region_add_subregion(&lpc->isa_fw, PNOR_SPI_OFFSET,
858-
&pnv->pnor->mmio);
859-
/*
860-
* Start disabled. The HIOMAP protocol will activate the mapping
861-
* with HIOMAP_C_CREATE_WRITE_WINDOW
862-
*/
863-
if (!hostboot_mode) {
864-
memory_region_set_enabled(&pnv->pnor->mmio, false);
865-
}
866-
867852
return isa_bus;
868853
}

0 commit comments

Comments
 (0)