Added Tilelink (TL-UL) #9
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hadirkhan10
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hadirkhan10
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hadirkhan10
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hadirkhan10
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hadirkhan10
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@shahzaibk23 please review the changes required before I can merge them..
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Changes made ✅ Shifted Due to use of Masked Memory 1 Test of Wishbone's Switch Harness was creating issues so I commented it for the time being :) |
hadirkhan10
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Jun 2, 2021
hadirkhan10
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hadirkhan10
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hadirkhan10
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hadirkhan10
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hadirkhan10
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Read/Write Operations of
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@shahzaibk23 did you re-run the tests to verify everything is working correctly? |
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All tests passed :) |
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This PR includes the Tilelink (TL-UL) implementation added alongside Wishbone in the caravan family, following the Adapter Template and Tilelink Protocols Strictly.
It is enriched with meaningful, self-explantory comments for better understanding (FOR OPEN SOURCE).
I have also globalized the
MemoryDumpFileHelpertrait ny creating acommonpackage insrc/tests/scala/and imported the traits in all the test files, where it was used.