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add path() method to python module #4616
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As a user, I expect these things below:
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Because ExternalProjectHolder already does
Into a generic interpreter object. This isn't a module, it's an object returned by a module, it also happens to be a special case of an ExternalProgram, which is a normal interpreter object. Let's treat it like one.
This would normally be exposed by the ExternalProgramHolder, but wasn't due to the implementation of the PythonInstallation module. Because of that I've duplicated the method so that we can add the FeatureNew decorator. Fixes mesonbuild#4070
This doesn't touch everything as it's just based on the python3 module tests, ported to the python module. It's still better than the one very basic test in the unit test module.
So this MR adds the As for |
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* Update external/mesa3d from branch 'pie-gsi' to de161277950520f511f210739d967c1cc3250129 - Merge "Merge branch 'aosp/master' into aosp/pie-gsi" into pie-gsi - Merge branch 'aosp/master' into aosp/pie-gsi BUG: 123765087 BUG: 123764798 (Milestone) BUG: 77276633 (OKR) Test: checkbuild, sort-of works on X11 with gpu_mode=drm_virgl Change-Id: Ia46a94d0b53f1848cc2308ef31ec184adf9dbc58 - Merge "Reapply fix for the git version header" - Reapply fix for the git version header Change-Id: I3b2be5e64c09e3184f132dc394cc69c929efb83b - Merge changes I468159d5,I1b68d1ab * changes: Fix ldap on OWNERS Merge remote-tracking branch 'aosp/upstream-19.1' into aosp/master - Merge "prebuild: Add cle v3d_packet_v*_pack.h" - Merge "prebuild: Add vc4 v3d_packet_v*_pack.h prebuilt generation and Android.mk changes" - Merge "Revert "HACK: mesa: android: disable vc4 usage of libexpat"" - Fix ldap on OWNERS Test: n/a Change-Id: I468159d50aac05e4ec097a462999a032dc9b2aba - Merge remote-tracking branch 'aosp/upstream-19.1' into aosp/master This merges current aosp/upstream-19.1 branch into aosp/master. For easier autditing/review, this branch matches the clean-rebase branch here: https://github.com/johnstultz-work/mesa/commits/aosp-rebase-19.1 Which is the result of rebasing the clean series here, which matches aosp/master: https://github.com/johnstultz-work/mesa/commits/aosp-rebase-19.0.3 Change-Id: I1b68d1abcd74deb0e4344abda749781922889504 Signed-off-by: John Stultz <john.stultz@linaro.org> --- v2: * Rebase aosp-rebase-19.1 onto latest 19.1.2 * Fixup checkbuild issues * Regenerate merge - docs: add sha256 checksums for 19.1.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: add release notes for 19.1.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Update version to 19.1.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - iris: Use a uint16_t for key sizes sizeof(struct brw_vs_prog_key) == 324. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 4633298fd62121a466884998cb64d7a5b5976fcd) - radv: Fix interactions between variable descriptor count and inline uniform blocks. Fixes: d7e6541cc72 "radv: Only allocate supplied number of descriptors when variable." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 8a053254b81497cb6b0708fe86986e461ee43771) - intel: fix wrong format usage Do not use the view format when filling the surface state. Fixes dEQP-VK.image.texel_view_compatible.compute.extended.texture.* Fixes: fb1350c76f1 ("intel: Add and use helpers for level0 extent") Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit e06bc0b16671b78032e06d9ddd547bb091501129) - spirv: Ignore ArrayStride in OpPtrAccessChain for Workgroup From OpPtrAccessChain description in the SPIR-V spec (1.4 rev 1): For objects in the Uniform, StorageBuffer, or PushConstant storage classes, the element’s address or location is calculated using a stride, which will be the Base-type’s Array Stride when the Base type is decorated with ArrayStride. For all other objects, the implementation will calculate the element’s address or location. For non-CL shaders the driver should layout the Workgroup storage class, so override any explicitly set ArrayStride in the shader. This currently fixes only the lower_workgroup_access_to_offsets case, which is used by anv. Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> (cherry picked from commit 050eb6389a8867e6173644fbb6b2d13ad0db454b) - prebuild: Add cle v3d_packet_v*_pack.h GENERATED! DO NOT REBASE! REGENERATE! Generated from prebuilt generation script. Signed-off-by: John Stultz <john.stultz@linaro.org> Change-Id: Ifcf88fea2268da17a732f5691533c7d9375d9c69 - prebuild: Add vc4 v3d_packet_v*_pack.h prebuilt generation and Android.mk changes Add v3d_packet_v*_pack.h file generation to the aosp-gen-prebuilt.sh script and rework the Android.mk file to copy the prebuilt file. Change-Id: Idfa51e226a23f67bb7a477b3e5de7fe4ddf8235a Signed-off-by: John Stultz <john.stultz@linaro.org> - Revert "HACK: mesa: android: disable vc4 usage of libexpat" This reverts commit 0ad61bc0ddba78f700af751514eecb0ee5e2494e. This change along with some missing prebuilt bits causes checkbuild to fail. So to fix this first, revert this change. Change-Id: Ibece4e88e361452d3ba8c1af6394c58e20a224ea Signed-off-by: John Stultz <john.stultz@linaro.org> - meson: Improve detection of Python when using Meson >=0.50. Previously, on systems where multiple versions of Python 3 (e.g. 3.6 and 3.7) are installed, wrong version of Python 3 could have been used. The proper fix requires availability of path() method in Meson's python module, which has been added in Meson 0.50: https://github.com/mesonbuild/meson/pull/4616 Distro Bug: https://bugs.gentoo.org/671308 Signed-off-by: Arfrever Frehtes Taifersar Arahesis <Arfrever@Apache.Org> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> v2: - Add missing `endif` keyword (Dylan) (cherry picked from commit b120a02b21791ef9898dd342af8102ec9f4d36d9) - meson: Search for execinfo.h Rather than checking __GLIBC__/__UCLIBC__ macros as a proxy for execinfo.h presence, just check directly. This allows the build to work on musl. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 10e8d466011076a0453368cb976d9f6b06af0e94) - util: Heap-allocate 256K zlib buffer The disk cache code tries to allocate a 256 Kbyte buffer on the stack. Since musl only gives 80 Kbyte of stack space per thread, this causes a trap. See https://wiki.musl-libc.org/functional-differences-from-glibc.html#Thread-stack-size (In musl-1.1.21 the default stack size has increased to 128K) [mattst88]: Original author unknown, but I think this is small enough that it is not copyrightable. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit fd7b7f14d857f96cf3b2e9d8405dbbfa30dc261a) - radv: Only allocate supplied number of descriptors when variable. Fixes: b5e04e9217b "radv: Support allocating variable size descriptor sets." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111019 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit d7e6541cc720a7d11d678adbeec7143b099127b0) - meson: GNU/kFreeBSD has DRM/KMS and requires -D_GNU_SOURCE This is a regression from the old autotools build system. Acked-by: Eric Engestrom <eric.engestrom@intel.com> Acked-by: Dylan Baker <dylan@pnwbakers.com> (cherry picked from commit 7389bf9761ae8ed7f28c631954c5d263263f3882) - vl: Use CS composite shader only if TEX_LZ and DIV are supported Enable the compute shader copositer only when TEX_LZ is supported by the driver. v2: Also check whether DIV is supported. https://bugs.freedesktop.org/show_bug.cgi?id=110783 Fixes: 9364d66cb7f7 gallium/auxiliary/vl: Add video compositor compute shader render Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 75d8b4e79542e08a42cab28378b830836f078eb5) - gallium: Add CAP for opcode DIV Not all drivers support TGSI_OPCODE_DIV, so we should have a cap to be able to check this. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 843723e2f7c79633cb0fe910b60684b8b2d289f6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/gallium/docs/source/screen.rst src/gallium/include/pipe/p_defines.h - intel/compiler: don't use byte operands for src1 on ICL The simulator complains about using byte operands, we also have documentation telling us. Note that add operations on bytes seems to work fine on HW (like ADD). Using dwords operands with CMP & SEL fixes the following tests : dEQP-VK.spirv_assembly.type.vec*.i8.* v2: Drop the GLK changes (Matt) Add validator tests (Matt) v3: Drop GLK ref (Matt) Don't mix float/integer in MAD (Matt) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> (v1) Reviewed-by: Matt Turner <mattst88@gmail.com> BSpec: 3017 Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 5847de6e9afe12bd29ad694a76860a0575ab4747) - Revert "meson: Add support for using cmake for finding LLVM" This reverts commit 5157a4276500c77e2210e853b262be1d1b30aedf. There is a meson bug that causes llvm to always be statically linked, which is obviously not what we want. I haven't had time to look into it yet, but for now let's just revert it. (cherry picked from commit 97c2c4546ca5d7c17f039dde9a6fd5957fb2364a) - Revert "iris/icl: Add WA_2204188704 to disable pixel shader panic dispatch" SLICE_COMMON_CHICKEN3 is a privileged register not accesible from userspace. This patch silences a simulator warning about it. We don't need to add this workaround in linux kernel as the WA description says it's fixed on latest stepping. This reverts commit 9c421d6b47e0c5f206959acd68814b63232946be. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit d96cba775413ab357194af96b20c2107a0155bd8) - Revert "anv/icl: Add WA_2204188704 to disable pixel shader panic dispatch" SLICE_COMMON_CHICKEN3 is a privileged register not accesible from userspace. This patch silences a simulator warning about it. We don't need to add this workaround in linux kernel as the WA description says it's fixed on latest stepping. This reverts commit 2be60e0c73ed1555a919c5725cc0cab119a2b6de. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 387e43b52fa2c17ae1cd3f95c7578407d9c4ef95) - Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch" SLICE_COMMON_CHICKEN3 is a privileged register not accesible from userspace. This patch silences a simulator warning about it. We don't need to add this workaround in linux kernel as the WA description says it's fixed on latest stepping. This reverts commit 85ecd14ef6a084f5e82860de6dbc79870b335682. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 7746d4edef5332777bd0206e836617879ad8bb70) - radeon/uvd: fix calc_ctx_size_h265_main10 Left shift was applied twice. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110702 Reviewed-by: Leo Liu <leo.liu@amd.com> Tested-by: <irherder@gmail.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit c81c784a4a05f8a957a649d73c8194247de47b56) - mesa: delete framebuffer texture attachment sampler views When a context is destroyed the destroy_tex_sampler_cb makes sure that all the sampler views created by that context are destroyed. This is done by walking the ctx->Shared->TexObjects hash table. In a multiple context environment the texture can be deleted by a different context, so it will be removed from the TexObjects table and will prevent the above mechanism to work. This can result in an assertion in st_save_zombie_sampler_view because the sampler_view owns a reference to a destroyed context. This issue occurs in blender 2.80. This commit fixes this by explicitly releasing sampler_view created by the destroyed context for all texture attachments. Fixes: 593e36f956 (st/mesa: implement "zombie" sampler views (v2)) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110944 Signed-off-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit c37f03d46480e73d7c0cbfe93e91cd8d69d47220) - meson: bump required libdrm version to 2.4.81 dbb4457d9858fa977246 started using drmDevicesEqual(), which was introduced in libdrm 2.4.81 We could either copy the function locally, or bump the required version. Since the function is non-trivial and 2.4.81 is old enough already, I suggesting the latter. Fixes: dbb4457d9858fa977246 ("egl: add EGL_EXT_device_drm support") Cc: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 5819bc0e5c1802e0c0fb7544468d5ff635e1b268) - radv: only enable VK_AMD_gpu_shader_{half_float,int16} on GFX9+ These two extensions are supported on GFX8 but the throughput of 16-bit floats/integers is same as 32-bit. Also, shaderInt16 is only enabled on GFX9+ for the same reason, be more consistent. This fixes a crash with Wolfenstein II because it expects shaderInt16 to be enabled when VK_AMD_gpu_shader_half_float is exposed. Note that AMDVLK only enables these extensions on GFX9+. Cc: 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit ef1787dbc95e138b782fef1fcc93279ccf0e4910) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/vulkan/radv_extensions.py - gallium: Make util_copy_image_view handle shader_access A while back, we added a new field, but failed to update the copier. I believe iris is the only current user of the new field, and it hasn't used the copier, so noone noticed. Fixes: 8b626a22b24 st/mesa: Record shader access qualifiers for images Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 255c71ec07ec1f3af5b996d7b19717014ba946d3) - isl: Don't align phys_level0_sa by block dimension Aligning phys_level0_sa by the compression block dimension prior to mipmap layout causes the layout of compressed surfaces to differ from the sampler's expectations in certain cases. The hardware docs agree: From the BDW PRM, Vol. 5, Compressed Mipmap Layout, The compressed mipmaps are stored in a similar fashion to uncompressed mipmaps [...] The following exceptions apply to the layout of compressed (vs. uncompressed) mipmaps: * [...] * The dimensions of the mip maps are first determined by applying the sizing algorithm presented in Non-Power-of-Two Mipmaps above. Then, if necessary, they are padded out to compression block boundaries. The last bullet indicates that alignment should not be done for calculating a miplevel's dimensions, but rather for determining miplevel placement/padding. Comply with this text by removing the extra alignment. Fixes some fbo-generatemipmap-formats piglit failures on all tested platforms (SNB-KBL). v2: - Note fixed platforms. - Update some consumers via a helper function. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 02f6995d76c9fa0fdbc7a89013f4968970ab016e) - intel: Add and use helpers for level0 extent Prepare for a bug fix by adding and using helpers which convert isl_surf::logical_level0_px and isl_surf::phys_level0_sa to units of surface elements. v2: - Update iris (Ken). - Update anv. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit fb1350c76f1525e6bd320cef62d55aff19ec3f05) - iris: Enable PIPE_CAP_SURFACE_REINTERPRET_BLOCKS This makes CompressedTexSubImage from a PBO source do proper GPU rendering to upload instead of stalling to map the PBO source on the CPU (then copying it on the CPU). Thanks Bas Nieuwenhuizen for pointing out that Vulkan includes this functionality, and to Jason Ekstrand for writing the code I adapted. Vulkan only supports a single layer, however, and this code tries to support multiple layers as long as it's miplevel 0. Improves performance in Sid Meier's Civilization VI: Average frame time (ms): -3.67423% +/- 1.46201% (n=5) 99th percentile frame time (ms): -5.09910% +/- 3.87874% (n=5) (cherry picked from commit a032a9665f275085c825b54b62128ae90adba1c6) - meson: Add support for using cmake for finding LLVM Meson has support for using cmake as a finder for some dependencies, including LLVM. Using cmake has a lot of advantages: it needs less meson maintenance to keep working (even for llvm updates); it works more sanely for cross compiles (as llvm-config is a compiled binary not a shell script). Meson 0.51.0 also has a new generic variable getter that can be used to get information from either cmake, pkg-config, or config-tools dependencies, which is needed for cmake. We continue to support using llvm-config if you don't have cmake installed, or if cmake cannot find a suitable version. Fixes: 0d59459432cf077d768164091318af8fb1612500 ("meson: Force the use of config-tool for llvm") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 5157a4276500c77e2210e853b262be1d1b30aedf) - intel/compiler: fix derivative on y axis implementation This rewrites the ddy in EXECUTE_4 mode with a loop to make it more obvious what is going on and also sets the group each of the 4 threads in the groups are supposed to execute. Fixes the following CTS tests : dEQP-VK.glsl.derivate.dfdyfine.dynamic_* Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Co-Authored-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Fixes: 2134ea380033d5 ("intel/compiler/fs: Implement ddy without using align16 for Gen11+") (cherry picked from commit 836225840c21dfb9ee77267e06e14bba781f69a1) - glsl: Fix round64 conversion function Fix round64 function to handle round to nearest even cases specially with positive and negative numbers with fraction part 0.5. v2: 1) Simplify unused bits (Elie Tournier) Fixes: KHR-GL45.gpu_shader_fp64.builtin.round_dvec2 KHR-GL45.gpu_shader_fp64.builtin.round_dvec3 KHR-GL45.gpu_shader_fp64.builtin.round_dvec4 KHR-GL45.gpu_shader_fp64.builtin.roundeven_double KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2 KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3 KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4 Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Elie Tournier <elie.tournier@collabora.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com> (cherry picked from commit 06807e1948f1bced9806b00908c892f1e3c3db5b) - i965: leaking of upload-BO with push constants In case of any enabled VS members from: uses_firstvertex, uses_baseinstance, uses_drawid, uses_is_indexed_draw leaks may happens. Call gen6_upload_push_constants allocates stage_stat->push_const_bo. It than takes pointer from push_const_bo to draw_params_bo (in the call brw_prepare_shader_draw_parameters by brw_upload_data) and do reference which finally haven't got unreferenced. Fixes leak: 136 bytes in 1 blocks are definitely lost in loss record 6 of 13 at 0x4C31B25: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) by 0xC2B64B7: bo_alloc_internal (brw_bufmgr.c:596) by 0xC2B6748: brw_bo_alloc (brw_bufmgr.c:672) by 0xC314BB3: brw_upload_space (intel_upload.c:88) by 0xC2EBBC5: gen6_upload_push_constants (gen6_constant_state.c:155) by 0xC9E4FA6: gen9_upload_vs_push_constants (genX_state_upload.c:3300) by 0xC2E0EDA: check_and_emit_atom (brw_state_upload.c:540) by 0xC2E0EDA: brw_upload_pipeline_state (brw_state_upload.c:659) by 0xC2E0FF1: brw_upload_render_state (brw_state_upload.c:681) by 0xC2C5D2D: brw_draw_single_prim (brw_draw.c:1052) by 0xC2C62CB: brw_draw_prims (brw_draw.c:1175) by 0xC488AD1: vbo_exec_vtx_flush (vbo_exec_draw.c:386) by 0xC485270: vbo_exec_FlushVertices_internal (vbo_exec_api.c:652) Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reported-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com> Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> (cherry picked from commit 1931c97a1dc71f8fb548a23247c2a0dd4793ad3c) - anv/descriptor_set: Only write texture swizzles if we have an image view When immutable samplers are set we call write_image_view with a NULL image view. This causes issues on IVB where we have to fake texture swizzling. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110999 Fixes: d2aa65eb18 "anv: Emulate texture swizzle in the shader when..." (cherry picked from commit 0a364a4a74e774030cde542ba8be90008b3f1211) - anv/cmd_buffer: Reuse gen8 Cmd{Set, Reset}Event on gen7 Modern DXVK requires event support [1], but looks like it only uses vkCmdSetEvent() + vkGetEventStatus(). So we can just borrow the relevant code from gen8, leaving CmdWaitEvents still unimplemented. [1] https://github.com/doitsujin/dxvk/commit/8c3900c533d83d12c970b905183d17a1d3e8df1f v2: Also move CmdWaitEvents into genX_cmd_buffer.c (Jason) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 6230bfeb656f1de598e8ed58cef548dc1c1781aa) - freedreno/a5xx: fix batch leak in fd5 blitter path Fixes: 3d198926a48 freedreno: use fd_bc_alloc_batch instead of fd_batch_create. Signed-off-by: Rob Clark <robdclark@chromium.org> (cherry picked from commit 927fb50727e6e6652c0e4ce300e098843ad12013) - glsl: Don't increase the iteration count when there are no terminators Incrementing the iteration count was intended to fix an off-by-one error when the first terminator was superseded by a later terminator. If there is no first terminator or later terminator, there is no off-by-one error. Incrementing the loop count creates one. This can be seen in loops like: do { if (something) { // No breaks or continues here. } } while (false); Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Tested-by: Abel Briggs <abelbriggs1@hotmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110953 Fixes: 646621c66da ("glsl: make loop unrolling more like the nir unrolling path") (cherry picked from commit ee1c69faddb3624ace6548dafaff50549a031380) - anv: Add HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED in vk_format When HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED is used, then the platform gralloc module will select a format based on the usage flags provided by the camera device and the other endpoint of the stream. The patch fixes crash in vulkan when the test is run with camera stream set to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED. Test: android.graphics.cts.CameraVulkanGpuTest#testCameraImportAndRendering on chromebook with camera HAL3. v2: use AHARDWAREBUFFER_FORMAT_IMPLEMENTATION_DEFINED and take AHARDWAREBUFFER_USAGE_CAMERA_MASK in to account (Gurchetan) Fixes: f1654fa7e31 "anv/android: support creating images from external format" Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com> Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit d94fca54203edc0b7fece6aa2dc8703ad4e93c79) - freedreno: Fix up end range of unaligned UBO loads. We need the constants uploaded to cover the NIR offset plus the size, not the aligned-down start of our upload range plus the size. Fixes mistaken UBO analysis with mat3 loads. Fixes: 893425a607a6 ("freedreno/ir3: Push UBOs to constant file") Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 56842d33d53f3ea76b9359e8ead2ea4487e62dc1) - freedreno: Fix UBO load range detection on booleans. NIR 1-bit bool dests will have a bit size of 1, and thus a calculated "bytes" of 0. load_ubo is always loading from dwords in the source. Fixes: 893425a607a6 ("freedreno/ir3: Push UBOs to constant file") Reviewed-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 5e7c96b95df0f2d792820a27b278a95a90893e4a) - docs: add sha256 checksums for 19.1.1 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: add release notes for 19.1.1 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Update version to 19.1.1 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - util/os_file: resize buffer to what was actually needed Fixes: 316964709e21286c2af5 "util: add os_read_file() helper" Reported-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 955c63d3643f30d7db0c5d16e06a5eda4f62f889) - iris: Fix iris_flush_and_dirty_history to actually dirty history. When I split iris_flush_and_dirty_history into two helper functions, I accidentally made it stop dirtying. Which was...sort of the point. Fixes: 21688a306b2 iris: Split iris_flush_and_dirty_for_history into two helpers. (cherry picked from commit 64fb20ed326fa0e524582225faaa4bb28f6e4349) [Juan A. Suarez: resoved trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/gallium/drivers/iris/iris_resource.c - glx: fix glvnd pointer types Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110709 Fixes: 22a9e00aab66d3dd6890 ("glx: Implement the libglvnd interface.") Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 65b016b1469574ab2e3b4d2c2706fd96c995fa9f) - radv: disable viewport clamping even if FS doesn't write Z This fixes new CTS dEQP-VK.pipeline.depth_range_unrestricted.*. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 0a313cc285c2939de9cac07f045b0b699bc208ca) - meson: Allow building radeonsi with just the android platform. Just as was allowed by autotools. Fixes: 108d257a168 "meson: build libEGL" Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit d1c04835ab273c5f9806fbe2095b1dd03f460833) - anv: Fix vulkan build in meson. Apparently the android part was never ported to meson. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 755c633b8d9c15227ad07bbc98f06627d4ecf55d) - radv: Fix vulkan build in meson. Apparently the android part was never ported to meson. CC: <mesa-stable@lists.freedesktop.org> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4c300bd328138949659892447e7e68028cc950cb) - radv: fix FMASK expand with SRGB formats Found while working on DCC for MSAA. Fixes: 6b976024a87 ("radv: add support for FMASK expand") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit a7f75377aba6853e08561acb9609c5e262e4d9a6) - egl: Don't add hardware device if there is no render node v2. Do not offer a hardware drm backed egl device if no render node is available. The current implementation will fail on this egl device. On top it issues a warning that is actually missleading. There are finally more error paths that can fail on the way to a hardware backed egl device. Fixing all of them would kind of require opening the drm device and see if there is a usable driver associated with the device. The taken approach avoids a full probe and fixes at least this kind of problem on kvm virtualization hosts I observe here. Fixes: dbb4457d985 ("egl: add EGL_EXT_device_drm support") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de> (cherry picked from commit 5743a36b2b32a91eaf82c8d109932fe4fea01233) - nouveau: fix frees in unsupported IR error paths. This is pointless in that we won't ever hit those paths in real life, but coverity complains. Fixes: f014ae3c7cce ("nouveau: add support for nir") Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (cherry picked from commit 93ba356544a16e1f2bb0be3550d3b24ec2e5b13a) - freedreno/a6xx: un-swap X24S8_UINT The stencil is actually in the .w component, but we used to use SWAP to remap the channels. This doesn't work when tiled/ubwc. Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d_array dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_cube dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d_array dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube dEQP-GLES31.functional.stencil_texturing.misc.base_level dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.sampler.uint_stencil Signed-off-by: Rob Clark <robdclark@chromium.org> (cherry picked from commit 4e72abcd9764cb791a6a6a7dcb903c9e23ebbedf) - glsl: Fix out of bounds read in shader_cache_read_program_metadata The VaryingNames array has NumVaryings entries. But BufferStride is a small array of MAX_FEEDBACK_BUFFERS (4) entries. Programs with more than 4 varyings would read out of bounds. Also, BufferStride is set based on the shader itself, which means that it's inherently already included in the hash, and doesn't need to be included again. At the point when shader_cache_read_program_metadata is called, the linker hasn't even set those fields yet. So, just drop it entirely. Fixes valgrind errors in KHR-GL45.transform_feedback.linking_errors_test. Fixes: 6d830940f78 glsl/shader_cache: Allow shader cache usage with transform feedback Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 3c10a2726bcf686f03e31e79e40786e3894ff063) - anv: Set STATE_BASE_ADDRESS upper bounds on gen7 This should fix floating-point border color on all gen7 HW. Integer is still thoroughly busted on gen7 because it doesn't exist on IVB and it's crazy on HSW. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 9672b7044cc329b94a72de9ec5bdda1895901304) - virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts When the host virglrenderer is an older version that doesn't check the sRGB write control feature, or when the guest kernel doesn't support CAPS v2, then the guest will only report support for GL 2.1 on a GL 3.3 host, even though it was supporting 3.3 with earlier guest mesa versions. By also checking the host feature check version this regression can be avoided. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110921 Fixes: 2845939d6a72 virgl: Set sRGB write control CAP based on host capabilities Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Chia-I Wu <olvaffe@gmail.com> (cherry picked from commit 2b87753a84da7a1bd8a84f26f3cd0e03cc52c930) - radv: Decompress DCC when the image format is not allowed for buffers. Otherwise the buffer loads/stores in the bufimage meta operations fail. If we decompress DCC then we can use the "canonical" format compatible with the not-supported format. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 410759091173fa61436ba46baeb20a79d5767849) - i965: support UYVY for external import only It is similar with YUYV Fixes: 165e704719b85c ("i965/i915: Add UYVY as the supported format") Signed-off-by: Haihao Xiang <haihao.xiang@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 8ead5bebdb5cedc5250116403166279b1b292a85) - intel/dump: fix segfault when the app hasn't accessed the device Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit f80679c8e8aa3f1ff17deef7163ad9429eb90f44) - freedreno/a5xx: Fix indirect draw max_indices calculation The number of elements to draw should not be affected by the offset. A similar fix was submitted for a6xx at 79180a05. Fixes these dEQP tests on a5xx: dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_separate_grid_500x500_drawcount_8 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_separate_grid_500x500_drawcount_2500 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawarrays_separate_grid_500x500_drawcount_2500 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawarrays_combined_grid_500x500_drawcount_2500 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_combined_grid_500x500_drawcount_8 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_combined_grid_500x500_drawcount_2500 Reviewed-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 3fb7b1fd350246c09ef014a9fb8a04728d66e88a) - v3d: fix checking twice auf flag Seems a C&P error, and should check for auf/muf. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110902 Fixes: 8f065596d22ab000c53f "v3d: Add an optimization pass for redundant flags updates." Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 17c2c9cd67797e8e741859015c123b26c4fa293f) - radv: Skip transitions coming from external queue. Transitions to external queue should do the transition & make sure it works on all queues. Fixes: 8ebc7dcb59a "radv: Allow fast clears with concurrent queue mask for some layouts." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 0667c1f14b06b9a748619a1a6ba3e03388fa868b) - st/mesa: Add rgbx handling for fp formats Add missing cases for fp32 and fp16 formats. Fixes: c68334ffc0a9 "st/mesa: add floating point formats in st_new_renderbuffer_fb()" Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 845ec8576a600ea54f80a2639e0466041f145ffa) - gallium/winsys/kms: Fix dumb buffer bpp The bpp in the dumb buffer creation request is hardcoded to 32, which is an incorrect assumption as the caller is free to pick any pipe format. Use the bpp supplied to us through util_format_get_blocksizebits(). Fixes: 3b176c441b "gallium: Add a dumb drm/kms winsys backed swrast provider" Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit ec0a68e50dd3ebfbeee77670d7d09184d0907ead) - util/futex: fix dangling pointer use Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110901 Fixes: 7dc2f4788288ec9c7ab6 "util: emulate futex on FreeBSD using umtx" Cc: Greg V <greg@unrelenting.technology> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 9996ddbb27c9eb39cd234a4abce6c3742572c770) - radv: fix VK_EXT_memory_budget if one heap isn't available When the visible VRAM size is equal to the VRAM size only two heaps are exposed. This fixes dEQP-VK.api.info.device.memory_budget. Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit d3781512468aa1c96e92cc6a99963cd0fed80d30) - radv: fix occlusion queries on VegaM The number of render backends is 16 but the enabled mask is 0xaaaa. As noticed by Bas, allowing disabled render backends might break the OCCLUSION_QUERY packet. We don't use it yet but keep this in mind. This fixes dEQP-VK.query_pool.* and dEQP-VK.multiview.*. Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 2ef9d2738c8905cb3a83baf14cc1d088786d57e3) - anv: do not parse genxml data without INTEL_DEBUG=bat This significantly slows down the CTS runs. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 32ffd90002b04b ("anv: add support for INTEL_DEBUG=bat") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (cherry picked from commit 93b93e5a9da31b3f7d722029e23609d8a187bf01) - r300g: restore performance after RADEON_FLAG_NO_INTERPROCESS_SHARING was added v1: Fix skipped slab allocators and the buffer cache. v2: Use only 1 domain for texture allocation v3: Added flag for the create_fence call too Based on Marek v1 and v2 proposed fixes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=1107812.patch Cc: 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit ffd2f948fee271cbbce93708fc508dab7cb5d14c) - docs: Add SHA256 sums for 19.1.0 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: Add release notes for 19.1.0 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Update version to 19.1.0 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - radv: Prevent out of bound shift on 32-bit builds. uintptr_t is 32-bits then and shifting it by 32 bits results in undefined behavior IIRC. Fixes: b3c8de1c55c "radv: save all descriptor pointers into the trace BO" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 39c71e002561052d0596200b2d0ebdb8cc39d862) - radv: fix setting CB_SHADER_MASK for dual source blending CB_SHADER_MASK was computed without the second color buffer format which looks totally wrong to me. While we are at it, copy a comment from RadeonSI. Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit e9316fdfd4899c269a19e106a6ffa4309ae48b27) - mapi: correctly handle the full offset table Earlier commit converted ES1 and ES2 to a new, much simpler, dispatch generator. At the same time, GL/glapi and the driver side are still using the old code. There is a hidden ABI between GL*.so and glapi.so, former referencing entry-points by offset in the _glapi_table. Hence earlier commit added the full table of entry-points, alongside a marker for other cases like indirect GL(X) and driver-size remapping. Yet the patches did not handle things fully, thus it was possible to get different interpretations of the dispatch table after the marker. This commit fixes that adding an indicative error message to catch future bugs. While here correct the marker (MAX_OFFSETS) comment. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110302 Fixes: cf317bf0937 ("mapi: add all _glapi_table entrypoints tostatic_data.py") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit a379b1c0ee31a792bba250cc466ad4b161a610ec) - mapi: add static_date offset to MaxShaderCompilerThreadsKHR As elaborated in the next patch, there is some hidden ABI that effectively require most entrypoints to be listed in the file. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110302 Cc: Marek Olšák <maraeo@gmail.com> Fixes: c5c38e831ee ("mesa: implement ARB/KHR_parallel_shader_compile") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 61960547df89809194583b7faf553a64b557ae96) - radv: fix alpha-to-coverage when there is unused color attachments When alphaToCoverage is enabled, we should always write the alpha channel of MRT0 if it's unused. This now matches RadeonSI. This fixes the new CTS: dEQP-VK.pipeline.multisample.alpha_to_coverage_unused_attachment.samples_*.alpha_invisible Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl (cherry picked from commit 91aa25f4625014ddf194578fc1c1d0a505e5f8db) - egl/x11: calloc dri2_surf so it's properly zeroed Commit 2282ec0a refactored drawable creation across various platforms into a new dri2_create_drawable helper function. The GBM code in platform_drm.c code passed in dri2_surf->gbm_surf as the loaderPrivate, while most other backends passed in dri2_surf directly. To try and handle this, the patch checked if dri2_surf->gbm_surf was non-NULL, and if so, presumed that the caller is the DRM platform and we should use the dri2_surf->gbm_surf pointer. This worked for most platforms, which calloc their dri2_surf structure, zeroing the data. Unfortunately, platform_x11.c used malloc, leaving most of the dri2_surf as garbage. In particular, dri2_surf->gbm_surf was often non-NULL, causing dri2_create_drawable to try and use it, passing a garbage pointer to the createNewDrawable hook, usually leading to a SIGBUS or SIGSEGV when trying to dereference that bad pointer. Since most callers calloc the data, make platform_x11.c follow suit. Fixes crashes with i915_dri.so when running dEQP-GLES2. Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit 4e3297f7d4d87618bf896ac503e1f036a7b6befb) - util/os_file: actually return the error read() gave us Fixes: 316964709e21286c2af5 "util: add os_read_file() helper" Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 7e35f20d44321b20777020ad067d39116d142013) - freedreno/a6xx: fix hangs with newer sqe fw With the newer (v1.76) fw, we were getting hangs (compared to older v1.66 fw). Re-work the GMEM code to structure things a bit closer to the blob. This moves some PKT7 packets from IB2 to IB1, which I think is what was confusing SQE and causing it to get stuck in an infinite loop. But in general structuring things at least closer to the same way blob does makes it easier to compare cmdstream. Note: this is a bit on the large side for what I'd normally consider for stable.. but right now it is looking like it is the newer fw that is headed for linux-firmware. This should defn have some soak time on master, but probably a good idea for this patch to end up in distro mesa builds by the time a630_sqe.fw hits linux-firmware. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit 958f6ffb60640c333a8b568c5f41467a1fecd1c0) - freedreno/a6xx: fix issues with gallium HUD In some cases the draw for the text wasn't working. This seems to be fixed by resyncing some of the "golded registers" from blob (initial values were based on somewhat older blob version). Perhaps good to have a bit of soak time on master, but would be good to eventually land in 19.x stable branches. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit b820c09fa8d1ce362cac0bc6e71693578d115563) - anv/cmd_buffer: Initalize the clear color struct for CNL+ On CNL+, the clear color struct is composed of RGBA channel values and fields which are either reserved by the HW or used to control fast-clears. Currently anv initializes the channel values to zero and allows the other fields to be undefined. Satisfy the MBZ field requirements by removing an optimization that doesn't hold true for CNL+ and pulling in the number of dwords to initialize from ISL. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit b4198e792c037dccb4d433abc1368bd8cc8d22ee) - svga: Remove unnecessary check for the pre flush bit for setting vertex buffers This fixes the missing rebind when the can_pre_flush bit is not set and the vertex buffers are the same as what have been sent. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Neha Bhende <bhenden@vmware.com> Signed-off-by: Charmaine Lee <charmainel@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> (cherry picked from commit f29b8fde915728134b2e2b912642fe573d405fcb) - winsys/svga/drm: Fix 32-bit RPCI send message Depending on whether compiled with frame-pointer or not, the temporary memory location used for the bp parameter in these macros are referenced relative to the stack pointer or the frame pointer. Hence we can never reference that parameter when we've modified either the stack pointer or the frame pointer, because then the compiler would generate an incorrect stack reference. Fix this by pushing the temporary memory parameter on a known location on the stack before modifying the stack- and frame pointers. Also in case of failuire RPCI channel is not closed which lead to vmx running out of channels. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> (cherry picked from commit 72fc886826e97a547828da427e1a157b83ba5ea0) - anv: Fix check for isl_fmt in assert Checking isl_fmt returned value in assert seems appropriate instead of format variable. Fixes: f1654fa7e31 "anv/android: support creating images from external format" Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> (cherry picked from commit d6724471a5775cbbeaafff1e1982f322b1d04c94) - nir/propagate_invariant: Don't add NULL vars to the hash table Fixes: 8410cf66d "nir/propagate_invariant: Skip unknown vars" Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit d96878a66a559f6690f01e82f06fcf92ae958d3c) - intel/perf: improve dynamic loading config detection We're currently trying to detect dynamic loading config support by trying to remove to test config (hard coded in the i915 driver) and checking we get ENOENT. This can fail if the test config was updated in Mesa but not yet in i915. A better way to do this is to pick an invalid ID and check for ENOENT. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit c1621274401b4bd2de7db1f7a813f6bfce8307f8) - intel/perf: fix EuThreadsCount value in performance equations EuThreadsCount is supposed to be the number of threads per EU, not the total number of threads in the whole device. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 1fc7b951278428 ("i965: Add Gen8+ INTEL_performance_query support") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 0430c6d18a90549b1dd40ea29a0c28d1a8e3a47d) - winsys/drm: Fix out of scope variable usage In this particular instance, struct member were used outside of the block where it was defined. Fix this by moving the definition outside of block. Signed-off-by: Deepak Rawat <drawat@vmware.com> Fixes: 569f83898768 ("winsys/svga: Add support for new surface ioctl, multisample pattern") Reviewed-by: Brian Paul <brianp@vmware.com> (cherry picked from commit 828e1b0b4c5eef96a7f9a64010532263430e1f13) - egl/dri: flesh out and use dri2_create_drawable() Wrap the loader->createNewDrawable() dance into a helper and use it throughout the codebase. This addresses a cases like surfaceless (SL) on swrast (SL on kms_swrast is fine) where we'd attempt using the wrong driver and crash out. v2: fixup quirky GBM (Mathias) v3: fixup GBM for real (Marek) Cc: mesa-stable@lists.freedesktop.org Cc: Mathias Fröhlich <Mathias.Froehlich@web.de> Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1) Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (v2) Signed-off-by: Marek Olšák <marek.olsak@amd.com> (v2) Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 2282ec0ad6581b588f7bdde1211357123316b4b9) - Update version to 19.1.0-rc5 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - freedreno: Fix GCC build error. ../src/freedreno/vulkan/tu_device.c:900:4: error: initializer element is not constant .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 }, ^ Suggested-by: Kristian Høgsberg <krh@bitplanet.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110698 Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit d4e70be7396b5330fca5b5ece2327a3e1c42b6e7) - ac: fix a typo in ac_build_wg_scan_bottom Cc: 19.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit c9b64b58dee89ac78d38358f7ebd75cf0d6b86dd) - ac/nir: mark some texture intrinsics as convergent Otherwise LLVM can sink them and their texture coordinate calculations into divergent branches. v2: simplify the conditions on which the intrinsic is marked as convergent v3: only mark as convergent in FS and CS with derivative groups Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 73dda85512942e67991a5fbc3c9a1714e7624d00) - radv: do not use gfx fast depth clears for layered depth/stencil images The driver should only fast depth clears with the graphics path when the view covers all image layers, otherwise this might corrupt layers when HTILE is enabled. Cc: 19.0 19.1 mesa-stable@lists.freedesktop.org Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 8a35eb0602735194f2976000ddff9dca2c8b5741) - intel/compiler: Fix assertions in brw_alu3 v2: Fix assertion for src1 (Ian Romanick) Fixes: 3b967e17 (intel/compiler: Avoid false positive assertions) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Suggested-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 3016756398c988e965ed189cfd99dc94ddb16626) - radeonsi: init sctx->dma_copy before using it Commit a1378639ab19 reordered context functions initializations but broke sctx->b.resource_copy_region init when using AMD_DEBUG=forcedma. In this case sctx->dma_copy was assigned a value after being used in: sctx->b.resource_copy_region = sctx->dma_copy; This commit moves the FORCE_DMA special case after sctx->dma_copy initialization. See https://bugs.freedesktop.org/show_bug.cgi?id=110422 Signed-off-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 4583f09caa5aef719a1eec282f24a86c789cbba6) - st/glsl: make sure to propagate initialisers to driver storage This essentially reverts 20234cfe3a20. Fixes piglit test: tests/spec/arb_get_program_binary/execution/uniform-after-restore.shader_test Fixes: 20234cfe3a20 "st/mesa: don't propagate uniforms when restoring from cache" Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110784 (cherry picked from commit fea36a8f43ea010ce0581a63b4b5fa1213a35982) - d3dadapter9: Revert to old throttling limit value Recently PIPE_CAP_MAX_FRAMES_IN_FLIGHT was changed from 2 to 1: 20909284f204091757c050aa40cfffaf3f981b9c No driver seems to overwrite the default value. One user reports severe regressions for some games. For now, revert to the value 2 for nine. Cc: "19.1" mesa-stable@lists.freedesktop.org Signed-off-by: Axel Davy <davyaxel0@gmail.com> (cherry picked from commit 5820ac6756898a1bd30bde04555437a55c378726) - u_blitter: don't fail mipmap generation for depth formats containing stencil Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=109754 Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (cherry picked from commit 4b11ed443b85e4fcddc5d0ef60dec096ecdb951e) - freedreno/a6xx: fix GPU crash on small render targets Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 8eaa2d502131bdce874603f522eabc4a5719f2e6) - freedreno/ir3: set more barrier bits Blob is also setting the .l bit, and it seems to solve some intermittent failures with a couple of deqp's: dEQP-GLES31.functional.image_load_store.2d.qualifiers.coherent_r32i dEQP-GLES31.functional.image_load_store.2d.qualifiers.volatile_r32f Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit f9fa456e1d09f1a6b2dccde056b3754f3f198ba7) - freedreno/ir3: fix input ncomp for vertex shaders ncomp is never set for vertex shaders, but a3xx and a4xx still use it. Fixes: 831f1a05c0d freedreno/ir3: rework varying packing Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Clark <robdclark@chromium.org> (cherry picked from commit 1db86d8b62860380c34af77ae62b019ed2376443) - nir: Actually propagate progress in nir_opt_move_load_ubo. Found with Jasons new metadata rework (https://gitlab.freedesktop.org/mesa/mesa/merge_requests/950). Fixes: af355aaa071 "nir: add nir_opt_move_load_ubo() optimization pass" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit e24a7840f60ac2290761ea2dc2831e8c3ba8bbfc) - swr/rast: fix 32-bit compilation on Linux Removing unused but problematic code from simdlib header to fix compilation problem on 32-bit Linux. Reviewed-by: Alok Hota <alok.hota@intel.com> (cherry picked from commit cf673747cefca03c2b672db6788c1ac2af6d9f33) - nir/dead_cf: Call instructions aren't dead When we inlined cf_node_has_side_effects into node_is_dead, all the conditions flipped and we forgot to flip one. Fortunately, it doesn't matter right now because no one uses this pass on shaders with more than one function. Fixes: b50465d197 "nir/dead_cf: Inline cf_node_has_side_effects" Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> (cherry picked from commit 8948048c6f01209bac0051e41cd84c38853bd251) - intel/fs: Do a stalling MFENCE in endInvocationInterlock() Fixes: 939312702e "i965: Add ARB_fragment_shader_interlock support" Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 9e403dc56e3ab702abc68fd65ed4ab324ba69e69) - intel/fs,vec4: Use g0 as the header for MFENCE We set header_present but then pass it some random garbage. Give it g0 instead. I'm not actually sure this does anything but g0 is the usual header data and this is what the windows driver does so it seems like a good idea. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 859de4a74857d2736f6e2dd9d2fd98b92bbc69d9) - iris: Don't assume UBO indices are constant It will be true for the constant/system value buffer because they use a constant zero but it's not true in general. If we ever got here when the source wasn't constant, nir_src_as_uint would assert. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 9dc57eebd578b976b94c54d083377ba0920d43a8) - nir/lower_non_uniform: safely iterate over blocks This fixes a problem where the same instruction gets replaced twice. This was happening when the replaced instruction would be at the end of a block. Replacement of : if ssa_8 { .... intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */ } Would be : if ssa_8 { loop { vec1 32 ssa_47 = intrinsic read_first_invocation (ssa_44) () vec1 1 ssa_48 = ieq ssa_47, ssa_44 if ssa_48 { loop { vec1 32 ssa_49 = intrinsic read_first_invocation (ssa_44) () vec1 1 ssa_50 = ieq ssa_49, ssa_44 if ssa_50 { intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */ break } else { .... } Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 3bd545764151 ("nir: Add a lowering pass for non-uniform resource access") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 366811bedb67ae7d31a02ea9b1f9fa942fb93602) - radv: allocate more space in the CS when emitting events If the driver waits for CP DMA to be idle and emit an EOP event we need more space. This fixes a crash with Quake Champions. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 47a10edefb3510d1cae071037dac78a46b31949b) - Update version to 19.1.0-rc4 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt" This reverts commit 55376cb31e2f495a4d872b4ffce2135c3365b873. It's been over a year and both QT 5.9.5 and 5.11.0 contained a fix for the original issue. It seems i965 only ever applied this workaround to the 18.0 branch. Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 11e16ca7ce0a702088b35ccccea85e243d801ef9) - anv: fix apply_pipeline_layout pass for arrays of YCbCr descriptors When using the binding tables to access arrays of YCbCr descriptors we did not consider the offset of the accessed element. We can't do a simple multiple because the binding table entries are tightly packed. For example element 0 of the array could use 2 entries/planes and element 1 could use 2 entries/planes. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 3bb8768b9d62 ("anv: toggle on support for VK_EXT_ycbcr_image_arrays") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit 2042f22e28b3a16ea137ac2083beaedd855b2c5f) - anv/android: fix missing dependencies issue during parallel build The libmesa_anv_gen* modules require anv_extensions.h, patch makes sure it gets generated as a dependency before building them. Signed-off-by: Chenglei Ren <chenglei.ren@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Cc: <mesa-stable@lists.freedesktop.org> (ch…
This started out life as an attempt to add a
path()
method to thePythonImplementation
, but ended up with a bunch of cleanups and some tests. The base of this is that for mesa we need to pass the path of the python binary tomeson.add_install_script
, which can be done with thepython3
module. I ended up doing a bunch of cleanups in the process. This fixes a difference between the python3 and python module for functionality.