AXI VIP DMA CDMA BRAM AXI4_IP综合验证
- 用vip验证axi4_lite和axi4_full还比较方便，但是用vip验证axi4_stream不太方便。
- 本设计，利用了dma+cdma+bram，通过vip来配置dma和cdma，来实现对axi4_stream和axi4_full的ip验证。
- 这个方案非常方便，比直接用vip验证axi4_stream和axi4_full方便很多，代码也简洁很多。
包含了vip, dma, cdma，以及3种axi4_ip：axi4_lite, axi4_full, axi4_stream
地址分配
################################################################
# This is a generated script based on design: system
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source system_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z020clg400-2
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name system
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:user:axi4_full_ip:1.0\
xilinx.com:user:axi4_lite_ip:1.0\
xilinx.com:user:axi4_stream_ip:1.0\
xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:axi_cdma:4.1\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:axi_vip:1.1\
xilinx.com:ip:blk_mem_gen:8.4\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
set clk [ create_bd_port -dir I -type clk clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {100000000} \
] $clk
set rst_n [ create_bd_port -dir I rst_n ]
# Create instance: axi4_full_ip_0, and set properties
set axi4_full_ip_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axi4_full_ip:1.0 axi4_full_ip_0 ]
# Create instance: axi4_lite_ip_0, and set properties
set axi4_lite_ip_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axi4_lite_ip:1.0 axi4_lite_ip_0 ]
# Create instance: axi4_stream_ip_0, and set properties
set axi4_stream_ip_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axi4_stream_ip:1.0 axi4_stream_ip_0 ]
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
# Create instance: axi_cdma_0, and set properties
set axi_cdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_cdma:4.1 axi_cdma_0 ]
set_property -dict [ list \
CONFIG.C_INCLUDE_DRE {1} \
CONFIG.C_INCLUDE_SG {0} \
CONFIG.C_M_AXI_MAX_BURST_LEN {256} \
] $axi_cdma_0
# Create instance: axi_dma_0, and set properties
set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm {0} \
CONFIG.c_include_sg {0} \
CONFIG.c_sg_include_stscntrl_strm {0} \
] $axi_dma_0
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {5} \
CONFIG.NUM_SI {3} \
] $axi_interconnect_0
# Create instance: axi_vip_0, and set properties
set axi_vip_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip:1.1 axi_vip_0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.INTERFACE_MODE {MASTER} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $axi_vip_0
# Create instance: blk_mem_gen_0, and set properties
set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
set_property -dict [ list \
CONFIG.Assume_Synchronous_Clk {true} \
CONFIG.EN_SAFETY_CKT {false} \
CONFIG.Enable_B {Use_ENB_Pin} \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.Port_B_Clock {100} \
CONFIG.Port_B_Enable_Rate {100} \
CONFIG.Port_B_Write_Rate {50} \
CONFIG.Use_RSTB_Pin {true} \
] $blk_mem_gen_0
# Create interface connections
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTB]
connect_bd_intf_net -intf_net axi_cdma_0_M_AXI [get_bd_intf_pins axi_cdma_0/M_AXI] [get_bd_intf_pins axi_interconnect_0/S02_AXI]
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi4_stream_ip_0/S00_AXIS] [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_cdma_0/S_AXI_LITE] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi4_full_ip_0/S00_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi4_lite_ip_0/S00_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
connect_bd_intf_net -intf_net axi_vip_0_M_AXI [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins axi_vip_0/M_AXI]
# Create port connections
connect_bd_net -net M01_ACLK_1 [get_bd_ports clk] [get_bd_pins axi4_full_ip_0/s00_axi_aclk] [get_bd_pins axi4_lite_ip_0/s00_axi_aclk] [get_bd_pins axi4_stream_ip_0/s00_axis_aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_cdma_0/m_axi_aclk] [get_bd_pins axi_cdma_0/s_axi_lite_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins axi_vip_0/aclk]
connect_bd_net -net rst_clk_100MHz_100M_peripheral_aresetn [get_bd_ports rst_n] [get_bd_pins axi4_full_ip_0/s00_axi_aresetn] [get_bd_pins axi4_lite_ip_0/s00_axi_aresetn] [get_bd_pins axi4_stream_ip_0/s00_axis_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_cdma_0/s_axi_lite_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_vip_0/aresetn]
# Create address segments
create_bd_addr_seg -range 0x00010000 -offset 0x42000000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs axi4_full_ip_0/S00_AXI/S00_AXI_mem] SEG_axi4_full_ip_0_S00_AXI_mem
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs axi4_lite_ip_0/S00_AXI/S00_AXI_reg] SEG_axi4_lite_ip_0_S00_AXI_reg
create_bd_addr_seg -range 0x00002000 -offset 0xC0000000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
create_bd_addr_seg -range 0x00010000 -offset 0x42000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs axi4_full_ip_0/S00_AXI/S00_AXI_mem] SEG_axi4_full_ip_0_S00_AXI_mem
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs axi4_lite_ip_0/S00_AXI/S00_AXI_reg] SEG_axi4_lite_ip_0_S00_AXI_reg
create_bd_addr_seg -range 0x00002000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
create_bd_addr_seg -range 0x00010000 -offset 0x42000000 [get_bd_addr_spaces axi_vip_0/Master_AXI] [get_bd_addr_segs axi4_full_ip_0/S00_AXI/S00_AXI_mem] SEG_axi4_full_ip_0_S00_AXI_mem
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces axi_vip_0/Master_AXI] [get_bd_addr_segs axi4_lite_ip_0/S00_AXI/S00_AXI_reg] SEG_axi4_lite_ip_0_S00_AXI_reg
create_bd_addr_seg -range 0x00002000 -offset 0xC0000000 [get_bd_addr_spaces axi_vip_0/Master_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
create_bd_addr_seg -range 0x00010000 -offset 0x41000000 [get_bd_addr_spaces axi_vip_0/Master_AXI] [get_bd_addr_segs axi_cdma_0/S_AXI_LITE/Reg] SEG_axi_cdma_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces axi_vip_0/Master_AXI] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
# Exclude Address Segments
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs axi_cdma_0/S_AXI_LITE/Reg] SEG_axi_cdma_0_Reg
exclude_bd_addr_seg [get_bd_addr_segs axi_cdma_0/Data/SEG_axi_cdma_0_Reg]
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
exclude_bd_addr_seg [get_bd_addr_segs axi_cdma_0/Data/SEG_axi_dma_0_Reg]
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs axi_cdma_0/S_AXI_LITE/Reg] SEG_axi_cdma_0_Reg
exclude_bd_addr_seg [get_bd_addr_segs axi_dma_0/Data_MM2S/SEG_axi_cdma_0_Reg]
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
exclude_bd_addr_seg [get_bd_addr_segs axi_dma_0/Data_MM2S/SEG_axi_dma_0_Reg]
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
说明：新建一个block_design后，将上面的代码直接copy到这里的tcl窗口，回车就可以直接生成前面的框图。相当的方便！
task init_bram;
int start_val;
base_addr = 32'hc0000000;
start_val=32'h1234_0000;
for(int i=0; i<128; i++)
master_agent.AXI4LITE_WRITE_BURST(base_addr + i*4,0,start_val+i,resp);
endtask
task test_axi4_stream_ip;
base_addr = 32'h40000000;
#10us
addr = 32'h00; data = 32'h0001_0003; //状态清除
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h30; data = 32'h0001_0003; //状态清除
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h18; data = 32'hC000_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
endtask 
第1部分是写入128words到bram的过程，每写入一个word需要9个cycles。总时间22.88us。
第2部分是配置dma，从bram传输128words到axi4_stream_ip的过程。总时间2.88us。 注意Max Burst Size会限制每次Burst的长度，会把比较长的传输自动 拆分为很多个较短的传输。注意这个拆分过程是自动的，非常方便。对于dma的配置来说，可以设置任意长度，无需关注底层的传输实现过程。
#10us
addr = 32'h00; data = 32'h0001_1003; //状态清除
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h30; data = 32'h0001_1003; //状态清除
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
如果设置MM2S_DMACR寄存器的第12位，那么可以开启中断功能。这样当传输结束之前会产生中断。产生中断的位置是可配置的。
task test_axi4_full_ip;
base_addr = 32'h41000000;
#200ns
addr = 32'h18; data = 32'hC000_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h20; data = 32'hC000_1000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
endtask 
task test_cdma_bram2axi_full;
base_addr = 32'h41000000;
//write burst
#200ns
addr = 32'h18; data = 32'hC000_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h20; data = 32'h4200_0000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
//read burst
#10us
addr = 32'h18; data = 32'h4200_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h20; data = 32'hC000_1000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
endtask 
从波形发现，从bram->axi_full_ip快很一倍，因为从bram可以连续读。 但是从axi_full_ip->bram不可以连续读，每读一个都有一拍的停顿。 另外，可以看到，无论是读还是写的数据，确实都经过了cdma这个ip，可以据此画出信号流。这可以把cdma的axi总线展开可以看到。
让我们再观察一下axi_full_ip的波形。我们可以有如下结论： addr/len/size/burst/strobe/last等信号都是广播信号，也就是任何一个master或者slave发起，都会呈现在总线的所有axi接口上。 只有valid/ready信号才是私有信号，是建立传输通道的信号。 比如这个地方，写axi_full_ip和读axi_full_ip的时刻，valid/ready信号有效的时刻如图中红色圈出所示。
假设我们修改cdma的长度，例如把axi_full_ip->bram的长度修改为128*32+33
task test_cdma_bram2axi_full;
base_addr = 32'h41000000;
//write burst
#200ns
addr = 32'h18; data = 32'hC000_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h20; data = 32'h4200_0000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
//read burst
#10us
addr = 32'h18; data = 32'h4200_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h20; data = 32'hC000_1000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
#200ns
addr = 32'h28; data = 32'd128*32+33; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
endtask 
前4次arlen=0xff=255，第5次arlen=0x08=8。总传输bytes数=（4*256+9）4=4129bytes。实际长度设置=32'd12832+33=4129。匹配！ 每次burst_len最大为256，这是axi4总线的规定。
task test_cdma_bram2axi_lite;
base_addr = 32'h41000000;
//fill axi_lite_ip regs
addr = 32'h18; data = 32'hC000_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h20; data = 32'h4300_0000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h28; data = 32'd32; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
//write burst with fixed reg
#10us
addr = 32'h00; data = 32'h0000_0020; //key_hole_wr=1
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h18; data = 32'hC000_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h20; data = 32'h4300_0000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
//read burst with fixed reg
#10us
addr = 32'h00; data = 32'h0000_0010; //key_hole_rd=1
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h18; data = 32'h4300_0000; //配置源地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h20; data = 32'hC000_1000; //配置目的地址
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
addr = 32'h28; data = 32'd128*4; //配置传输长度，以byte为单位
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
endtask 
- 先给axi-lite-ip的前8个regs写入值
- 设置key-hole-wr功能，开始cdma写，可以看到。写入的值固定往0x4300_0000地址写，也就是reg0写。因此只有reg0的值在变化。
- 设置key-hole-rd功能，开始cdma读，可以看到。读出的值固定是0x4300_0000地址的值，因此读出的值始终不变。
这就充分展示了key-hole的功能。