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Add restrictions to RiscvMachine
#11
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The conditions given in `RiscvMachine` are not satisfying. See issue mit-plv#11
The conditions given in `RiscvMachine` are not satisfying. See issue mit-plv#11
I tried to implement restrictions on the reservation mechanism (instructions LR and SC). I added the following lines to
And I found the constraints unsatisfiable for the instance in Does anyone have an idea for a better approach to formalise my intent, or do I wish for something impractical and impossible? I’d like to only allow instances of In my repo is a branch “MemoryReservation” containing a commit with my work. |
By the way: Except the trouble with the restrictions, memory reservations themselves are not problematic. I’ll rework the commit and produce an implementation of the A extension. So at least something useful will come out of this. |
@samuelgruetter, is |
Long-ish answer on what The point of the But in order to prove anything interesting about a RiscV machine, we have to make assumptions about the behavior of these primitives. For instance, the bedrock2 compiler assumes that memory behaves like a partial map, ie. if you write and then read the same address, you get back the value you wrote. Encoding these assumptions can be done by implementing the typeclass I realize this is not documented well enough. As you're working with this code, you'll probably learn about quite some design considerations, and if you'd be willing to write that up, that would be very welcome 😉 |
Thanks for the explanation. It’s very difficult understanding the relations between the different files, because I have to look into each of them and now know by heart, what each more or less does and at what level of abstraction it works. I’d very much like to see this code more documented, because the project interests me, but I don’t know if I’ll be able to find the time to do it myself. At bare minimum, our conversations document a bit what the code does. I don’t know how much time I have to offer, but there will be some opportunities throughout the year where I can lend a hand and a head. I am not yet used to collaborating with others (on GitHub or elsewhere). But I’ll try it. |
Something nice about the technique of separating the functions (like in |
Closing this issue because I see that you already solved this question, although I don’t yet understand the solution. |
The current definition of
RiscvMachine
allows some nonsensical instances, which don’t conform to the RISC-V spec. For example is it not necessary for register reads throughgetRegister
to return a previously written value. Another sensible restriction is, that reading and writing from independent locations must commute.A difficulty of writing the restrictions is, that they may constrain logging of program execution, depending on how logging is implemented. (I don’t understand it yet) If logging changes the internal state of the monad, then the restrictions must allow these to happen.
I’m not used to monads and am not sure how the restrictions can be formalized just-right. I’ll upload some attempts.
Concerning memory accesses:
Although the restrictions would be simpler, if the
load*
andstore*
operations would be defined in terms of byte-sized operations, it wouldn’t be sensible to do this, without riscv-semantics doing the same. A benefit the current approach is that logging can tell the difference between accesses of different size. This would be more difficult, if an instance ofRiscvMachine
could only provide byte-sized operations.Edit: I learned, that I haven’t yet understood how logging works.
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