GitHub - mtayler/ceng450_processor: 16 bit custom processor designed with Xilinx ISE in VHDL

mtayler / ceng450_processor Public

16 bit custom processor designed with Xilinx ISE in VHDL

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Name		Name	Last commit message	Last commit date
Latest commit History 39 Commits
netgen/par		netgen/par
planAhead_run_1		planAhead_run_1
planAhead_run_2		planAhead_run_2
planAhead_run_3		planAhead_run_3
.gitignore		.gitignore
1test16_sq2.vhd		1test16_sq2.vhd
2test16_Fct.vhd		2test16_Fct.vhd
3test16_Fct.vhd		3test16_Fct.vhd
ALU8_16.vhd		ALU8_16.vhd
ALU8_16TB.vhd		ALU8_16TB.vhd
ALU_RF_TB.vhd		ALU_RF_TB.vhd
Display_Controller.vhd		Display_Controller.vhd
PROC_16TB.vhd		PROC_16TB.vhd
RAM_16.vhd		RAM_16.vhd
RF8_16.vhd		RF8_16.vhd
RF8_16TB.vhd		RF8_16TB.vhd
alu.spl		alu.spl
alu.sym		alu.sym
alu.ucf		alu.ucf
alu.xdl		alu.xdl
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
mem_int.vhd		mem_int.vhd
motherboard.ucf		motherboard.ucf
motherboard.vhd		motherboard.vhd
motherboard.xdl		motherboard.xdl
motherboard_reportgen.xrpt		motherboard_reportgen.xrpt
pa.fromHdl.tcl		pa.fromHdl.tcl
pa.fromNcd.tcl		pa.fromNcd.tcl
pa.fromNetlist.tcl		pa.fromNetlist.tcl
planAhead.ngc2edif.log		planAhead.ngc2edif.log
planAhead_pid3093.debug		planAhead_pid3093.debug
planAhead_pid37864.debug		planAhead_pid37864.debug
processor.cgc		processor.cgc
processor.cgp		processor.cgp
processor.ipf		processor.ipf
processor.ucf		processor.ucf
processor.vhd		processor.vhd
processor.wcfg		processor.wcfg
processor.xise		processor.xise
processor_routed.wcfg		processor_routed.wcfg
ram_flist.txt		ram_flist.txt
ram_xmdf.tcl		ram_xmdf.tcl
register_file.spl		register_file.spl
register_file.sym		register_file.sym
register_file_alu.xise		register_file_alu.xise