INTRO

This is my OpenLane repository in which i perform the synthesis of different design modules.

SYNTHESIS: synthesis is the process of converting RTL(synthesizable verilog code)to technology specific gate level netlist.

NETLIST: It is basically a combination of sequential elements and their logical connectivity

HOW YOU CAN USE THIS REPO

clone my repo

https://github.com/muhammadtalhasami/openlane

OPENLANE_INSTALLATION

The short version is, to install the OpenLane environment...

1. Get Docker
2. Get Python 3.6 or higherUbuntu)
   • On Ubuntu, you may also need to install venv: apt-get install python3-venv

Run the following commands in your terminal:

1): cd $HOME
2): git clone https://github.com/The-OpenROAD-Project/OpenLane
3): cd OpenLane
4): make
5): make test

After the installation is completed :

now simply run this on your terminal:-

1): cd OpenLane
2): make mount

now you can use it

NOTE: you might face some problem while installing docker please follow the above giving link for that carefully.

GUI_OF_DESIGN

for this you can used klayout

follow this command on your terminal:-

1): sudo apt-get install klayout

CONTRIBUTION

We welcome contributions from the community to enhance the repository with new projects, improvements, and additional resources. If you have ideas or suggestions, feel free to fork the repository, make your changes, and submit a pull request.