Multiple ports same line declaration support

src/VerilogParser.yy

@@ -87,13 +87,14 @@ size_t portIndex = 0;
 %type<naja::verilog::Identifier> parameter_identifier;
 
 %type<naja::verilog::Port> port_declaration
+%type<naja::verilog::Ports> internal_ports_declaration
 %type<naja::verilog::Port::Direction> port_type_io
 %type<naja::verilog::Net::Type> net_type;
 %type<naja::verilog::Range> range;
 %type<naja::verilog::Range> range.opt
 %type<naja::verilog::Range> constant_range_expression.opt;
 %type<naja::verilog::Identifier> net_identifier;
-%type<naja::verilog::Identifiers> list_of_net_identifiers;
+%type<naja::verilog::Identifiers> list_of_identifiers;
 %type<naja::verilog::RangeIdentifiers> net_lvalue;
 %type<naja::verilog::RangeIdentifiers> list_of_net_lvalues;
 %type<naja::verilog::Identifier> module_instance;
@@ -151,6 +152,13 @@ port_declaration: port_type_io range.opt identifier {
   $$ = Port($3, $1, $2);
 }
 
+internal_ports_declaration: port_type_io range.opt list_of_identifiers {
+  constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
+  for (auto portIdentifier: $3) {
+    constructor->internalModuleImplementationPort(Port(portIdentifier, $1, $2));
+  }
+}
+
 port_type_io
   : INOUT_KW  { $$ = naja::verilog::Port::Direction::InOut; } 
   | INPUT_KW  { $$ = naja::verilog::Port::Direction::Input; }
@@ -194,18 +202,18 @@ module_or_generate_item:
 
 module_or_generate_item_declaration: net_declaration;
 
-net_declaration: net_type range.opt list_of_net_identifiers ';' {
+net_declaration: net_type range.opt list_of_identifiers ';' {
   for (auto netIdentifier: $3) {
     constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
     constructor->addNet(Net(netIdentifier, $2, $1));
   }
 }
 
-list_of_net_identifiers
+list_of_identifiers
 : net_identifier {
   $$ = { $1 };
 }
-| list_of_net_identifiers ',' net_identifier {
+| list_of_identifiers ',' net_identifier {
   $1.push_back($3);
   $$ = $1;
 }
@@ -362,11 +370,7 @@ port: identifier {
   constructor->internalModuleInterfaceSimplePort($1);
 }
 
-module_item: port_declaration {
-  constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
-  constructor->internalModuleImplementationPort($1);
-} ';'
-| non_port_module_item;
+module_item: internal_ports_declaration ';' | non_port_module_item;
 
 list_of_module_items: module_item | list_of_module_items module_item;
 

src/VerilogTypes.h

@@ -91,6 +91,8 @@ struct Port {
   std::string getString() const;
 };
 
+using Ports = std::vector<Port>;
+
 struct Net {
   class Type {
     public:

test/CMakeLists.txt

@@ -13,6 +13,7 @@ set(tests
   NajaVerilogTest6.cpp
   NajaVerilogTest7.cpp
   NajaVerilogTest8.cpp
+  NajaVerilogTest9.cpp
   NajaVerilogTestMultipleFiles.cpp
   NajaVerilogTestErrors.cpp
 )

test/NajaVerilogTest9.cpp

@@ -0,0 +1,70 @@
+// SPDX-FileCopyrightText: 2024 The Naja verilog authors <https://github.com/najaeda/naja-verilog/blob/main/AUTHORS>
+//
+// SPDX-License-Identifier: Apache-2.0
+
+#include "gtest/gtest.h"
+
+#include <filesystem>
+#include <fstream>
+
+#include "VerilogConstructor.h"
+
+using namespace naja::verilog;
+
+#include "VerilogConstructorTest.h"
+
+#ifndef NAJA_VERILOG_BENCHMARKS
+#define NAJA_VERILOG_BENCHMARKS "Undefined"
+#endif
+
+TEST(NajaVerilogTest9, test) {
+  VerilogConstructorTest constructor;
+  std::filesystem::path test9Path(
+      std::filesystem::path(NAJA_VERILOG_BENCHMARKS)
+      / std::filesystem::path("benchmarks")
+      / std::filesystem::path("test9.v"));
+
+  constructor.setFirstPass(true);
+  constructor.parse(test9Path);
+  ASSERT_EQ(1, constructor.modules_.size());
+  EXPECT_TRUE(constructor.modules_[0]->nets_.empty());
+  EXPECT_TRUE(constructor.modules_[0]->assigns_.empty());
+  EXPECT_TRUE(constructor.modules_[0]->instances_.empty());
+  auto test = constructor.modules_[0];
+  const auto& ports = constructor.modules_[0]->ports_;
+  ASSERT_EQ(7, constructor.modules_[0]->ports_.size());
+  EXPECT_EQ(naja::verilog::Identifier("i1", false), ports[0].identifier_);
+  EXPECT_EQ(naja::verilog::Identifier("i2%", true), ports[1].identifier_);
+  EXPECT_EQ(naja::verilog::Identifier("i3", false), ports[2].identifier_);
+  EXPECT_EQ(naja::verilog::Identifier("o1", false), ports[3].identifier_);
+  EXPECT_EQ(naja::verilog::Identifier("o2", false), ports[4].identifier_);
+  EXPECT_EQ(naja::verilog::Identifier("io1", false), ports[5].identifier_);
+  EXPECT_EQ(naja::verilog::Identifier("io2", false), ports[6].identifier_);
+
+  EXPECT_EQ(naja::verilog::Port::Direction::Input, ports[0].direction_);
+  EXPECT_EQ(naja::verilog::Port::Direction::Input, ports[1].direction_);
+  EXPECT_EQ(naja::verilog::Port::Direction::Input, ports[2].direction_);
+  EXPECT_EQ(naja::verilog::Port::Direction::Output, ports[3].direction_);
+  EXPECT_EQ(naja::verilog::Port::Direction::Output, ports[4].direction_);
+  EXPECT_EQ(naja::verilog::Port::Direction::InOut, ports[5].direction_);
+  EXPECT_EQ(naja::verilog::Port::Direction::InOut, ports[6].direction_);
+
+  EXPECT_FALSE(ports[0].range_.valid_);
+  EXPECT_FALSE(ports[1].range_.valid_);
+  EXPECT_FALSE(ports[2].range_.valid_);
+  EXPECT_TRUE(ports[3].range_.valid_);
+  EXPECT_EQ(3, ports[3].range_.msb_);
+  EXPECT_EQ(0, ports[3].range_.lsb_);
+  EXPECT_TRUE(ports[4].range_.valid_);
+  EXPECT_EQ(3, ports[4].range_.msb_);
+  EXPECT_EQ(0, ports[4].range_.lsb_);
+  EXPECT_FALSE(ports[5].range_.valid_);
+  EXPECT_FALSE(ports[6].range_.valid_);
+
+  constructor.setFirstPass(false);
+  constructor.parse(test9Path);
+  ASSERT_EQ(1, constructor.modules_.size());
+  EXPECT_TRUE(constructor.modules_[0]->nets_.empty());
+  EXPECT_TRUE(constructor.modules_[0]->assigns_.empty());
+  EXPECT_TRUE(constructor.modules_[0]->instances_.empty());
+}

test/benchmarks/test9.v

@@ -0,0 +1,8 @@
+//multiple ports on the same line or multi-line
+
+module test(i1, \i2% , i3, o1, o2, io1, io2);
+  input i1, \i2% , i3;
+  output [3:0] o1,
+   o2;
+  inout io1, io2;
+endmodule