Student in Sangmyung Univ. I am interested in semiconductor front-end development. (Verilog, ASIC, FPGA, logic design ...etc)
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Sangmyung Univ.
- Republic Of Korea
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15:20
(UTC +09:00)
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verilog_arithmetic_module
verilog_arithmetic_module Publicverilog 32-bit integer arithmetic module design
Verilog 2
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