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1. Constraint-Manager Constraint-Manager Public

   Automatic interface constraint generator for FPGAs

   Python 1

2. vunit vunit Public

   Forked from VUnit/vunit

   VUnit is a unit testing framework for VHDL/SystemVerilog

   VHDL 2

3. VHDL-LS/rust_hdl VHDL-LS/rust_hdl Public

   Rust 343 65

4. symbiflow-arch-defs symbiflow-arch-defs Public

   Forked from f4pga/f4pga-arch-defs

   FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

   Python

5. ghdl/ghdl ghdl/ghdl Public

   VHDL 2008/93/87 simulator

   VHDL 2.4k 362

6. jeremiah-c-leary/vhdl-style-guide jeremiah-c-leary/vhdl-style-guide Public

   Style guide enforcement for VHDL

   Python 191 39