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naming optimizations #17

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Nic30 opened this issue Jan 14, 2019 · 0 comments
Open
50 of 52 tasks

naming optimizations #17

Nic30 opened this issue Jan 14, 2019 · 0 comments

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@Nic30
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Nic30 commented Jan 14, 2019

  • Prefix for HCL objects needs to be specific so it is more easy to automatically update code after library updates
    • visually separation of normal Python objects and HCL
    • simplifies search in code
  • Names of signal, interface or component

    • Involves: BasicRtlSimProxy, RtlSignal, HwIO, HwModule
    • now it is not clear what the name actually means
      • .name -> ._name - logical name, name from user description
      • ._name -> ._hdlName - physical name, full name with resolved name collisions etc.
  • Backward type reference of signals and constant

  • type property name is too long
    ._dtype -> ._ht
  • Split HConst and HVar classes (because of performance reasons)
def tv(signal):
    return signal._dtype.getConstCls()

class RtlSignalOps():
    def __invert__(self):
        return self.naryOp(AllOps.NOT, tv(self).__invert__)

# currently the const class contains code also for signal/variable operator
class BitsConst:
    def __invert__(self):
        if isinstance(self, HConst):
            return Bits3val.__invert__(self)
        else:
            ...
  • Bits -> HBits (act as an int but it is not named int to avoid things like float inheriting from int)
  • hwt.synthesizer.unit.Unit -> hwt.hModule.HwModule (Using module stem because it is more widely used)
    • ._interfaces -> ._hwIOs
    • ._subunits -> ._subHwModules
    • ._params -> ._hwParams
    • ._paramsShared() -> ._hwParamsShared()
  • Interface -> HwIO
  • Signal -> HwIOSignal (adding HwIO so user do not think that this is the signal instance which should be normally used for communication inside of module)
  • Param -> HwParam
  • HValue -> HConst (same convention as in LLVM)
  • Operator -> HOperatorNode
  • OpDefinition -> HOperatorNodeDef
  • AllOps -> HwtOps
  • UniqList -> SetList (same convention as in LLVM)
  • SimTestCase.u -> SimTestCase.dut (replacing u after Unit -> HModule)
  • EmptyUnit -> hwtLib.abstract.emptyHModule.EmptyHModule
  • hwt.synthesizer.utils -> hwt.synth
  • HsStructIntf -> HwIOStructVldRd
  • StructIntf -> HwIOStruct
  • VldSyncedStructIntf -> HwIOStructVld
  • RdSyncedStruct -> HwIOStructRd
  • HdlType_to_Interface -> HdlType_to_HwIO
  • Interface_to_HdlType -> HwIO_to_HdlType
  • DifferentialIntf -> HwIODifferentialSig
  • RegCntrl -> HwIORegCntrl
  • TristateSig -> HwIOTristateSig
  • UnionSink -> HwIOUnionSink
  • UnionSource -> HwIOUnionSource
  • RdSynced -> HwIODataRd
  • RdSync -> HwIORdSync
  • VldSynced -> HwIODataVld
  • VldSync -> HwIOVldSync
  • Handshaked -> HwIODataVldRd
  • HandshakeSync -> HwIOVldRdSync
  • Clk -> HwIOClk
  • Rst -> HwIORst
  • Rst_n -> HwIORst_n
  • ReqDoneSync -> HwIOReqDoneSync
  • BramPort_withoutClk -> HwIOBramPort_noClk
  • BramPort -> HwIOBramPort
  • FifoWriter -> HwIOFifoWriter
  • FifoReader -> HwIOFifoReader
  • AxiStream -> Axi4Stream
  • hwtLib.amba.axi_intf_common -> hwtLib.amba.axi_common
  • walkPhysInterfaces -> HwIO_walkSignals
  • walkFlatten -> HwIO_walkFlatten
  • packHwIO -> HwIO_pack
  • connectPacked -> HwIO_connectPacked
  • IntfIpMetaNotSpecified -> IntfIpMetaNotSpecifiedError

flatten to parent:

  • move constants from hwt.synthesizer.rtlLevel.constants, hwt.hdl.constants to hwt.constants
  • hwt.synthesizer.interfaceLevel.interfaceUtils
  • hwt.synthesizer.rtlLevel.signalUtils
    • walkers -> rtlSignalWalkers
    • ops -> rtlSignalOps
  • hwt.synthesizer.hObjList -> hwt.hObjList
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